CPU Server Physical Design Methodology, Infrastructure and Automation Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$209,300–$313,900 / yr
Posted
4 days ago
Freshness
Confirmed live yesterday
Closes
Mar 10, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $208k
This role $262k
$131k most similar roles pay here $334k

This role pays more than 88% of similar roles. Most pay $168,425–$248,400 — the shaded band above. At the midpoint, this role pays about $262k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 631 open roles on FindRole.

Listed pay typically runs $143,400–$219,600 across 611 roles with salary data.

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At a glance

TL;DR · CPU Server Physical Design Methodology, Infrastructure and Automation Engineer

As a CPU Server Physical Design Methodology, Infrastructure and Automation Engineer, you will join the CPU Engineering team to lead critical design efforts for multi-core CPU operations. You will be responsible for developing and verifying high-performance, low-power CPU designs while solving complex problems related to design completeness, functionality, power, and performance. Your daily work involves collaborating with cross-functional teams to define requirements and trade-offs from conceptualization through post-silicon validation. You will also author detailed technical documentation for complex architectures. To succeed, you must possess expertise in computer architecture, micro-architecture, logic design, and circuits. The role requires proficiency in high-level programming languages like C and C++, scripting languages such as Python or Perl, and industry-standard tools for synthesis, place, route, and design verification, alongside experience with Verilog and VHDL for waveform debugging.

What you'll do

  • Develop and verify high-performance, low-power CPU designs using advanced knowledge of computer architecture and logic design.
  • Solve complex problems regarding design completeness, functionality, power, and performance for multi-core CPU operations.
  • Define requirements, specifications, and trade-offs such as performance, power, and cost with cross-functional teams.
  • Manage the entire design process from initial conceptualization and feasibility to pre-silicon verification and post-silicon validation.
  • Create detailed technical documentation including feature descriptions, architectural plans, and verification test plans for complex designs.
  • Provide supervision and guidance to other team members while working independently on high-priority tasks.
  • Communicate complex information and negotiate with stakeholders to influence key organizational decisions.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of relevant engineering experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of relevant engineering experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant engineering experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (preferred).
  • 10+ years of work experience with high-performance microprocessor design (preferred).
  • 10+ years of work experience with high level programming, scripting languages, simulators, and waveform debugging tools (preferred).
  • 10+ years of work experience with industry standard tools for synthesis, place/route, design verification, simulation, emulation, formal verification, or silicon validation (preferred).
  • 10+ years of experience in creating functional models, checkers, test plans, and/or test generation (preferred).
  • 3+ years experience working in a large matrixed organization (preferred).
  • 1+ year of work experience in a role requiring interaction with senior leadership (preferred).

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