CPU Physical Electrical Analysis Engineer

Apple Inc

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Work type: On-site
Location: Beaverton, OR
Posted: 17 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Similar $205k

$136k most similar roles pay here $282k

This listing doesn't post a salary. Most similar roles pay $168,000–$241,750.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · CPU Physical Electrical Analysis Engineer

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As a CPU Physical Electrical Analysis Engineer, you will join the hardware team to drive block and top-level design of power-grid and analysis of high performance compute blocks within the EMIR, SIGEM, and Reliability space. Your daily responsibilities involve driving electrical verification closure, managing power grid construction and implementation using PNR tool environments, and collaborating multi-functionally with CAD vendors, methodology teams, and SoC level teams to ensure design sign-off. You will utilize industry standard tools such as Siemens, Ansys Redhawk, Seascape, or Cadence Voltus. The role requires expertise in STA, computer architecture, and RISC pipelines for GPU, neural network, or CPU PNR blocks. Technical skills include C/C++, along with the ability to develop automation scripts and perform data analysis using TCL, Python, Perl, matplotlib, and pandas.

Skills

EMIR SIGEM Power Grid Design PNR STA TCL Python Perl C++ Ansys Redhawk Seascape Cadence Voltus Matplotlib Pandas Data Analysis Computer Architecture RISC Pipelines

What you'll do

Drive block and top-level EMIR and electrical verification closure.
Design, construct, and implement power grids using existing infrastructures or custom PNR tool solutions.
Perform analysis of high-performance compute blocks in the EMIR, SIGEM, and Reliability spaces.
Collaborate with CAD/EDA vendors to ensure the fidelity of analysis results.
Work with methodology teams to develop solutions for unique use cases.
Coordinate with implementation teams to drive design and sign-off closure.
Ensure IP delivery meets quality standards and schedules at the SoC level.

What we're looking for

Minimum of a Bachelor's degree and 10+ years of relevant industry experience.
Experience with PNR design implementation and STA.
Knowledge of computer architecture and RISC pipelines with experience in compute-oriented block implementation (preferred).
Experience in TCL-based automation with PNR and STA tools (preferred).
Familiarity with industry standard tools such as Siemens, Ansys Redhawk, Seascape, or Cadence Voltus (preferred).
Working knowledge of C/C++ (preferred).
Ability to write and maintain scripts in TCL, Python, or Perl (preferred).
Experience with data analysis techniques using Python, Perl, matplotlib, or pandas (preferred).

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