CPU Design Timing Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type
On-site
Location
—
Salary
$150,400–$277,600 / yr
Posted
15 days ago
Freshness
Confirmed live today

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $209k
This role $214k
$135k most similar roles pay here $293k

This role pays more than 60% of similar roles. Most pay $168,200–$250,000 — the shaded band above. At the midpoint, this role pays about $214k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · CPU Design Timing Engineer

The CPU Design Timing Engineer is responsible for the timing closure of a project, working closely with implementation teams and micro-architects to drive success. The role involves collaborating with the CAD team to develop timing flows, including writing scripts to improve analysis flows and engineer efficiency. Day-to-day tasks involve performing timing analysis, construction, and modification of timing flows while addressing noise analysis and variation modeling for high speed digital designs like CPUs. Required technical skills include proficiency in static timing analysis, TCL, Perl, or Python, along with experience in tools such as PrimeTime or Tempus. The role also requires knowledge of physical design methodology including logic synthesis, PnR, parasitic extraction, and logic equivalence while navigating deep sub-micron technologies and scaling trends to solve complex hardware engineering challenges.

More like this

Similar roles

CPU Design Timing Engineer

Apple Inc

Santa Clara, CA 15 days ago $184,700–$324,800
Static Timing Analysis PrimeTime Tempus TCL Python Perl SDC RTL Physical Design Logic Synthesis PnR Parasitic Extraction clock-domain crossing Assertion Based Verification
10+ yrs exp