CPU Design Timing Engineer

As the CPU Design Timing Engineer, you will join the hardware team to manage all aspects of timing closure for complex projects. You will collaborate closely with micro-architects and implementation engineers to drive timing results while working with the CAD team to develop timing flows and scripts that improve analysis efficiency. Your daily work involves performing timing analysis across multiple clock and power domains, managing noise analysis, and implementing variation modeling. The role requires proficiency in static timing analysis tools like PrimeTime or Tempus, along with expertise in TCL, Perl, or Python for scripting. You will utilize SDC commands for clock definitions and constraints while navigating deep sub-micron technologies. This position focuses on solving critical timing challenges within high-speed digital designs, specifically addressing the technical complexities of CPU microarchitecture and clock-domain crossing.