CAD Engineer - Design Verification Methodology

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Waltham, MA
Salary: $165,800–$292,400 / yr
Posted: 149 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $229k

$120k most similar roles pay here $311k

This role pays more than 86% of similar roles. Most pay $162,375–$214,000 — the shaded band above. At the midpoint, this role pays about $229k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · CAD Engineer - Design Verification Methodology

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CAD Engineer – Design Verification Methodology will join the Silicon Technologies group as a member of the CAD team to develop, maintain, and enhance sophisticated software systems for regression-testing silicon designs in software simulation. The role involves finding and reporting defects in chip designs to ensure successful tape-outs while collaborating with EDA vendors to incorporate new capabilities into commercial tools. The position requires proficiency in Python programming and experience debugging vendor tool problems. Preferred skills include knowledge of TCL, Perl, Verilog, SystemVerilog, VHDL, C, and C++. Candidates may also utilize simulation tools like VCS, Xcelium, or Modelsim, along with Cadence or Synopsys Emulation tools. The work focuses on the technical challenge of building robust regression systems to support design verification and chip design engineering efforts for high-performance, power-efficient system-on-chip products.

Skills

Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL

What you'll do

Develop, maintain, and enhance sophisticated software systems for regression-testing silicon designs.
Identify and report defects in chip designs during the software simulation phase.
Diagnose root causes of complex technical problems within the CAD team.
Collaborate with EDA vendors to integrate new tool capabilities and resolve technical issues.
Implement new functionality to solve emerging problems or optimize existing methodologies.
Provide technical guidance and support to engineers facing design verification challenges.
Utilize Python, TCL, or Perl to develop and maintain internal tools.

What we're looking for

Minimum of a BS degree and 10 years of relevant experience.
Experience developing, maintaining, and enhancing existing systems for regressing RTL.
Proficiency in Python programming is required.
Experience debugging vendor tool problems.
Knowledge of Verilog and SystemVerilog; familiarity with VHDL is a plus.
Experience with VCS, XCelium, or Modelsim simulation tools.
Experience with Cadence or Synopsys Emulation tools.
Preferred degrees include MSEE, CE, or CS.

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