CAD Engineer - Design Verification Methodology

Apple Inc

Confirmed live yesterday Low trust

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Work type: On-site
Location: Austin, TX
Posted: 149 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $188k

$129k most similar roles pay here $236k

This listing doesn't post a salary. Most similar roles pay $162,375–$214,000.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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TL;DR · CAD Engineer - Design Verification Methodology

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As a CAD Engineer – Design Verification Methodology within the Silicon Technologies group, you will develop, maintain, and enhance sophisticated software systems used for regression-testing silicon designs in software simulation. Your primary responsibility involves identifying and reporting defects in chip designs to ensure successful tape-outs of high-performance, power-efficient processors and system-on-chip architectures. You will collaborate with EDA vendors to integrate new capabilities into commercial tools while diagnosing root causes of complex technical problems for the broader engineering team. The role requires proficiency in Python, with additional experience in TCL, Perl, C, or C++. You will work within a domain involving RTL regression systems and hardware verification. Preferred skills include knowledge of Verilog, SystemVerilog, VHDL, and familiarity with tools such as VCS, Xcelium, Modelsim, Cadence, Synopsys Emulation, Verdi, and Indago.

Skills

Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL

What you'll do

Develop, maintain, and enhance sophisticated software systems for regression-testing silicon designs.
Identify and report defects in chip designs during the software simulation phase.
Diagnose root causes of complex technical problems within the CAD team.
Collaborate with EDA vendors to integrate new capabilities and resolve tool issues.
Implement new functionality to solve emerging problems or optimize existing methodologies.
Provide technical guidance and support to engineers across the Design Verification teams.

What we're looking for

Bachelor's degree required; MSEE, CE, or CS degrees are preferred.
Minimum of 10 years of relevant experience.
Experience developing, maintaining, and enhancing existing systems for regressing RTL.
Proficiency in Python programming is required.
Experience debugging vendor tool problems.
Knowledge of Verilog and SystemVerilog; familiarity with VHDL is a plus.
Experience with VCS, Xcelium, or Modelsim simulation tools.
Experience with Cadence or Synopsys Emulation tools.

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