CAD Engineer – Design Verification Methodology

Apple Inc

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 57 days ago
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $185k

$126k most similar roles pay here $229k

This listing doesn't post a salary. Most similar roles pay $156,000–$213,743.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · CAD Engineer – Design Verification Methodology

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As a CAD Engineer at Apple, you will join an elite team dedicated to designing verification methodologies for silicon designs. Your primary responsibilities include developing, maintaining, and enhancing software systems used in regression testing to identify defects in chip designs through simulation. You will collaborate with EDA vendors to integrate new tool capabilities and resolve issues, ensuring the continuous improvement of these critical systems. Essential skills include Python programming, experience with RTL regression systems, and debugging vendor tools. Preferred qualifications encompass knowledge in Verilog, SystemVerilog, VCS, XCelium, Modelsim, Cadence, Synopsys Emulation tools, and familiarity with AI/ML techniques. Your role is pivotal in supporting Apple’s design verification and chip engineering efforts on a large scale.

Skills

Python TCL Perl Verilog SystemVerilog VHDL VCS XCelium Modelsim Cadence Synopsys Verdi Indigo C C++

What you'll do

Develop, maintain, and enhance software systems for regression-testing Apple’s silicon designs.
Diagnose root causes of complex problems in chip design verification processes.
Collaborate with EDA vendors to integrate new tool capabilities and resolve issues.
Guide engineers in resolving defects found during software simulation testing.
Implement new functionality to optimize existing methods in regression systems.

What we're looking for

Minimum 10 years of relevant experience in developing and maintaining regression systems for RTL
Expertise in Python programming and debugging vendor tool issues
Experience implementing new functionality to solve emerging problems or optimize existing methods
Strong knowledge in Verilog, SystemVerilog, and familiarity with VHDL
Familiarity with VCS, XCelium, Modelsim, Cadence, and Synopsys Emulation tools
Excellent communication skills and prior customer support experience preferred

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