CAD Engineer - Design Verification Methodology

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $150,400–$277,600 / yr
Posted: 148 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $214k

$122k most similar roles pay here $294k

This role pays more than 76% of similar roles. Most pay $162,375–$214,000 — the shaded band above. At the midpoint, this role pays about $214k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · CAD Engineer - Design Verification Methodology

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CAD Engineer – Design Verification Methodology joins the Silicon Technologies group to develop, maintain, and enhance sophisticated software systems for regression-testing silicon designs in software simulation. The role focuses on identifying and reporting defects in chip designs to ensure successful tape-outs of high-performance, power-efficient system-on-chip products. Key responsibilities include diagnosing root causes of complex problems, collaborating with EDA vendors to integrate new tool capabilities, and implementing functionality to solve emerging issues or optimize existing methods. The position requires a Python programming background and involves working with tools such as Synopsys VCS, Xcelium, or Modelsim. Candidates may also utilize TCL, Perl, Verilog, SystemVerilog, VHDL, Verdi, Indago, C, and C++. This role provides critical support for design verification and chip design engineering efforts by building the infrastructure necessary to validate complex hardware designs.

Skills

Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium ModelSim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence

What you'll do

Develop, maintain, and enhance software systems for regression-testing silicon designs in software simulation.
Identify and report defects in chip designs to ensure successful tape-outs of high-performance SoCs.
Design and innovate the next generation of automated regression systems.
Diagnose root causes of complex technical problems and provide guidance to other engineers.
Collaborate with EDA vendors to integrate new tool capabilities and resolve software issues.
Implement new functionality to solve emerging problems or optimize existing design verification methods.
Write and maintain scripts or Makefiles to build simulation models from RTL.

What we're looking for

Minimum of a BS degree and 3 years of relevant experience.
Proficiency in Python programming.
Experience developing, maintaining, and enhancing systems for regressing RTL.
Knowledge of Verilog and SystemVerilog.
Experience debugging vendor tool problems.
Familiarity with tools such as Synopsys VCS, Xcelium, or Modelsim.
Preferred degrees include MSEE, CE, or CS.
Proficiency in additional languages like TCL, Perl, C, or C++ is a plus.

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