CAD Engineer – Design Verification Methodology

Apple Inc

Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $147,400–$272,100 / yr
Posted: 56 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $184k

This role $210k

$120k most similar roles pay here $288k

This role pays more than 74% of similar roles. Most pay $155,218–$213,743 — the shaded band above. At the midpoint, this role pays about $210k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · CAD Engineer – Design Verification Methodology

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Senior Hardware Verification Engineer needed for the cutting-edge semiconductor design team. This role involves developing and executing verification plans to ensure high-quality chip designs meet performance criteria, focusing on creating comprehensive test benches and simulations using industry-standard tools. Daily tasks include writing scripts in Python to automate build processes, collaborating with cross-functional teams to identify and resolve issues, and maintaining simulation models from RTL descriptions. Ideal candidates have a strong background in electrical engineering or computer science, along with experience using Synopsys VCS, XCelium, or Modelsim for verification purposes. Knowledge of scripting languages like Python and familiarity with Makefiles are crucial for building efficient simulation environments.

Skills

Python Synopsys_VCS XCelium Modelsim Makfile RTL

What you'll do

Develop and maintain Python scripts for hardware verification.
Write or enhance scripts to build simulation models from RTL code.
Utilize Synopsys VCS, XCelium, or Modelsim for verification tasks.
Ensure the accuracy and efficiency of simulation model builds.
Collaborate on improving existing Makefiles for automation purposes.

What we're looking for

Minimum BS degree and 3 years of relevant experience required.
Strong Python programming background necessary.
MSEE/CE/CS degree preferred but not mandatory.
Experience with Synopsys VCS, XCelium, or Modelsim beneficial.
Proficiency in writing or maintaining scripts or Makefiles for simulation models advantageous.

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