CAD Engineer - Design Verification Methodology

Apple Inc

Confirmed live 2 days ago Low trust

Quick summary

Work type: On-site
Location: Waltham, MA
Salary: $134,700–$249,500 / yr
Posted: 148 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k

This role $192k

$121k most similar roles pay here $263k

This role pays more than 62% of similar roles. Most pay $162,000–$214,000 — the shaded band above. At the midpoint, this role pays about $192k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · CAD Engineer - Design Verification Methodology

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As a CAD Engineer – Design Verification Methodology, you will join the Silicon Technologies group to develop, maintain, and enhance sophisticated software systems used for regression-testing silicon designs in software simulation. Your primary role involves identifying and reporting defects in chip designs to ensure successful tape-outs of high-performance, power-efficient processors and system-on-chip architectures. You will collaborate with EDA vendors to integrate new tool capabilities and resolve complex technical issues while providing guidance to the broader engineering team. The role requires proficiency in Python, with additional experience in TCL, Perl, C, or C++. Candidates may also utilize Verilog, SystemVerilog, VHDL, Synopsys VCS, Xcelium, Modelsim, Verdi, or Indago. You will solve critical problems related to RTL regression systems and implement new functionalities to optimize existing methods within the design verification domain.

Skills

Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium Modelsim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence

What you'll do

Develop, maintain, and enhance sophisticated software systems for regression-testing silicon designs.
Identify and report defects in chip designs during the software simulation phase.
Diagnose root causes of complex technical problems within the CAD team.
Collaborate with EDA vendors to integrate new capabilities into commercial tools.
Implement new functionality to solve emerging problems or optimize existing methods.
Provide technical guidance and support to engineers facing design verification challenges.
Write and maintain scripts or Makefiles to build simulation models from RTL.

What we're looking for

Minimum of a BS degree and 3 years of relevant experience.
Proficiency in Python programming.
Experience developing, maintaining, and enhancing systems for regressing RTL.
Knowledge of Verilog and SystemVerilog, with familiarity in VHDL.
Experience debugging vendor tool problems and interacting with EDA vendors.
Familiarity with simulation tools such as Synopsys VCS, Xcelium, or Modelsim.
Preferred degrees include MSEE, CE, or CS.
Knowledge of TCL, Perl, C, C++, or experience with AI/ML is preferred.

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