CAD Engineer - Design Verification Methodology

Apple Inc

Confirmed live yesterday Low trust

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Work type: On-site
Location: Beaverton, OR
Posted: 148 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $188k

$129k most similar roles pay here $236k

This listing doesn't post a salary. Most similar roles pay $162,375–$214,000.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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TL;DR · CAD Engineer - Design Verification Methodology

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As a CAD Engineer – Design Verification Methodology within the Silicon Technologies group, you will develop, maintain, and enhance sophisticated software systems used for regression-testing silicon designs in software simulation. Your primary responsibility involves identifying and reporting defects in chip designs to ensure successful tape-outs of high-performance, power-efficient processors and system-on-chip architectures. You will collaborate with EDA vendors to integrate new capabilities into commercial tools while diagnosing root causes of complex problems to support the broader design engineering efforts. The role requires proficiency in Python, with additional experience in TCL, Perl, C, or C++. You will work within a technical environment involving Verilog, SystemVerilog, and VHDL, utilizing tools such as Synopsys VCS, Xcelium, Modelsim, Verdi, and Indago to solve critical problems related to RTL regression and simulation model construction.

Skills

Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium Modelsim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence

What you'll do

Develop, maintain, and enhance sophisticated software systems for regression-testing silicon designs.
Identify and report defects in chip designs during the software simulation phase.
Design and implement next-generation regression systems based on innovative technical insights.
Diagnose root causes of complex technical problems to provide guidance to other engineers.
Collaborate with EDA vendors to integrate new capabilities into commercial tools and resolve issues.
Implement new functionality to solve emerging problems or optimize existing methodologies.
Build and maintain scripts or Makefiles to build simulation models from RTL.

What we're looking for

Bachelor's degree and at least 3 years of relevant experience are required.
A Master's degree in Electrical Engineering, Computer Engineering, or Computer Science is preferred.
Proficiency in Python programming is required.
Experience with TCL or Perl scripting is preferred.
Knowledge of Verilog and SystemVerilog is preferred, with familiarity in VHDL as a plus.
Experience with Synopsys VCS, Xcelium, or Modelsim tools is preferred.
Experience developing and maintaining systems for regressing RTL is preferred.
Knowledge of C and C++ programming languages is preferred.

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