CAD Engineer - Design Verification Methodology

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $184,700–$324,800 / yr
Posted: 149 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $255k

$116k most similar roles pay here $347k

This role pays more than 98% of similar roles. Most pay $162,375–$214,000 — the shaded band above. At the midpoint, this role pays about $255k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · CAD Engineer - Design Verification Methodology

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CAD Engineer – Design Verification Methodology works within the Silicon Technologies group to develop, maintain, and enhance sophisticated software systems used for regression-testing silicon designs in software simulation. The role focuses on identifying and reporting defects in chip designs to ensure successful tape-outs of high-performance, power-efficient processors and system-on-chip designs. Key responsibilities include diagnosing root causes of complex problems, guiding other engineers, and collaborating with EDA vendors to integrate new capabilities into commercial tools. Required technical skills include a Python programming background and experience regressing RTL and debugging vendor tool issues. Preferred qualifications include proficiency in TCL, Perl, C, or C++, knowledge of Verilog, SystemVerilog, or VHDL, and familiarity with simulation tools like VCS, Xcelium, Modelsim, Verdi, or Indago. The role also values experience with Cadence or Synopsys Emulation tools and artificial intelligence.

Skills

Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL

What you'll do

Develop, maintain, and enhance sophisticated software systems for regression-testing silicon designs.
Identify and report defects in chip designs during the software simulation phase.
Diagnose root causes of complex technical problems within the CAD team.
Collaborate with EDA vendors to integrate new tool capabilities and resolve technical issues.
Implement new functionality to solve emerging problems or optimize existing methodologies.
Provide technical guidance and support to engineers facing design verification challenges.

What we're looking for

Minimum of a BS degree and 10 years of relevant experience.
Experience developing, maintaining, and enhancing existing systems for regressing RTL.
Experience debugging vendor tool problems.
Proficiency in Python programming is required.
Preferred degrees include MSEE, CE, or CS.
Knowledge of Verilog and SystemVerilog; familiarity with VHDL is a plus.
Experience with VCS, XCelium, or Modelsim simulation tools.
Experience with Cadence or Synopsys Emulation tools.

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