CAD Engineer - Design Verification Methodology

Apple Inc

Confirmed live 2 days ago Low trust

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Work type: On-site
Location: Austin, TX
Posted: 148 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Similar $188k

$129k most similar roles pay here $236k

This listing doesn't post a salary. Most similar roles pay $162,375–$214,000.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

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TL;DR · CAD Engineer - Design Verification Methodology

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As a CAD Engineer – Design Verification Methodology within the Silicon Technologies group, you will develop, maintain, and enhance sophisticated software systems used for regression-testing silicon designs in software simulation. Your primary responsibility involves identifying and reporting defects in chip designs to ensure successful tape-outs of high-performance, power-efficient processors and system-on-chip architectures. You will collaborate with EDA vendors to integrate new capabilities into commercial tools while providing technical guidance to engineers across the extended CAD team. The role requires proficiency in Python, with additional experience in TCL, Perl, C, or C++. You will work within a domain focused on hardware design verification, utilizing tools such as Synopsys VCS, Xcelium, or Modelsim. Knowledge of Verilog, SystemVerilog, and VHDL is relevant for solving complex problems related to RTL regression systems and simulation model construction.

Skills

Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium Modelsim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence

What you'll do

Develop, maintain, and enhance sophisticated software systems for regression-testing silicon designs.
Identify and report defects in chip designs during the software simulation phase.
Design next-generation regression systems based on innovative ideas and technical insights.
Diagnose root causes of complex problems to support design verification engineering efforts.
Collaborate with EDA vendors to integrate new tool capabilities and resolve technical issues.
Implement new functionality to solve emerging problems or optimize existing methodologies.
Write and maintain scripts or Makefiles to build simulation models from RTL.

What we're looking for

Bachelor's degree and at least 3 years of relevant experience are required.
A background in Python programming is required.
Experience developing, maintaining, and enhancing systems for regressing RTL is preferred.
Knowledge of Verilog and SystemVerilog is preferred, with VHDL as a plus.
Experience with Synopsys VCS, Xcelium, or Modelsim is preferred.
Proficiency in TCL, Perl, C, or C++ is preferred.
Experience debugging vendor tool problems and implementing new functionality to solve emerging problems is preferred.
Familiarity with Verdi, Indago, artificial intelligence, and machine learning is preferred.

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