Senior to Staff Design Verification Engineer

Qualcomm

Confirmed live 2 days ago Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $121,800–$182,600 / yr
Posted: 9 days ago
Freshness: Confirmed live 2 days ago
Closes: Apr 21, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $202k

This role $152k

$109k $243k

below market most similar roles pay here above market

This role pays less than 87% of similar roles. Most pay $176,043–$227,300 — the blue band above. At the midpoint, this role pays about $152k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 594 open roles on FindRole.

Listed pay typically runs $147,900–$219,400 across 568 roles with salary data.

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At a glance

TL;DR · Senior to Staff Design Verification Engineer

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ASICS Design Verification Engineer-Senior to Staff joins the ASICS Engineering group to manage the complete verification lifecycle from system-level concept to tape out and post-silicon support. The role focuses on comprehensive pre-silicon test planning for digital power IPs, including testbench development, coverage development, and assertion model development. Key responsibilities involve deploying power-aware UPF verification flows and developing automation to improve verification efficiency. Candidates must utilize advanced verification methodologies such as SystemVerilog-UVM, formal verification, and property checking. Required technical skills include experience with ASIC design and verification tools, RTL languages like SystemVerilog, Verilog, or VHDL, and programming in C or C++. Preferred competencies include scripting with Perl or Python, knowledge of AMBA Bus protocols like AXI, AHB, and APB, and object-oriented programming concepts.

What does a Design Verification Engineer earn in California?

Median $199500 from 61 postings across 7 companies.

See salary data

Skills

SystemVerilog UVM Verilog VHDL Python C++ C Perl Formal Verification UPF AMBA AXI AHB APB ASIC Design RTL Object-oriented programming Automation

What you'll do

Perform comprehensive pre-silicon test planning for digital power IPs.
Develop testbenches using SystemVerilog-UVM methodologies.
Create coverage models and assertion models for verification.
Execute formal verification through property checking.
Deploy and manage power-aware UPF verification flows and methodologies.
Develop automation tools to improve verification efficiency.
Support the complete verification lifecycle from system-level concept to post-silicon.

What we're looking for

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, or integration experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, or integration experience.
PhD in Science, Engineering, or a related field.
Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a closely related field (preferred).
6+ years of experience with ASIC design and verification tools, techniques, and methodology (preferred).
6+ years of experience with digital design concepts and RTL languages such as SystemVerilog, Verilog, or VHDL (preferred).
6+ years of experience with computer architecture, OOP concepts, and C or C++ programming skills (preferred).
6+ years of experience with SystemVerilog testbench development, UVM/OVM methodologies, and scripting in Perl or Python (preferred).

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