Design Verification Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $101,400–$152,200 / yr
Posted: 10 days ago
Freshness: Confirmed live 2 days ago
Closes: Apr 20, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k

This role $127k

$86k $245k

below market most similar roles pay here above market

This role pays less than 97% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $127k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 594 open roles on FindRole.

Listed pay typically runs $147,900–$219,400 across 568 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The ASICS Design Verification Engineer joins the ASICS Engineering team to manage the complete verification lifecycle from system-level concept to tape out and post-silicon support. The role involves comprehensive pre-silicon test planning for digital power IPs, including testbench development, coverage development, and assertion model development. Key responsibilities include deploying power-aware UPF verification flows and developing automation to improve verification efficiency. Candidates must utilize SystemVerilog-UVM, formal verification property checking, and RTL languages such as Verilog or VHDL. Proficiency in C, C++, and scripting with Perl or Python is required. The position addresses technical challenges in digital design concepts and computer architecture fundamentals, specifically focusing on the verification of digital power IP components within the broader ASIC design and verification methodology.

What does a Design Verification Engineer earn in California?

Median $199500 from 61 postings across 7 companies.

See salary data

Skills

SystemVerilog UVM Verilog Python C++ Formal Verification UPF Perl AMBA AXI AHB APB VHDL Object-oriented programming RTL

What you'll do

Perform comprehensive pre-silicon test planning for digital power IPs.
Develop testbenches using SystemVerilog-UVM methodologies.
Create coverage models and assertion models for verification.
Execute formal verification and property checking.
Deploy and manage power-aware UPF verification flows.
Develop automation scripts to improve verification efficiency.
Provide post-silicon support for digital power IPs.

What we're looking for

Bachelor's degree in Engineering, Science, or a closely related field.
1+ years of experience with ASIC design and verification tools, techniques, and methodology.
Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a closely related field (preferred).
2+ years of experience with ASIC design and verification tools, techniques, and methodology (preferred).
2+ years of experience with digital design concepts and RTL languages such as SystemVerilog, Verilog, or VHDL (preferred).
2+ years of experience with computer architecture fundamentals, OOP concepts, and C or C++ programming skills (preferred).
2+ years of experience with developing block-level testbench environments using SystemVerilog (preferred).
2+ years of experience with verification methodologies such as UVM or OVM and Assertion Based Formal Verification (preferred).

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