Senior ASIC Verification Engineer

Nvidia

Quick summary

Work type
On-site
Location
Durham, NC · Madison, AL · Hillsboro, OR
Salary
$136,000–$218,500 / yr
Posted
130 days ago

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k
This role $177k
$126k most similar roles pay here $228k

This role pays more than 54% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

As a Senior Verification Engineer on NVIDIA’s Memory Management Unit team, you will work closely with architects and designers across sites to verify the world’s leading GPUs. Your responsibilities include defining verification scope, developing testbenches, BFMs, checkers, and monitors, implementing comprehensive test plans, and ensuring coverage closure. You will also contribute to the strategic direction of verification methodologies. Ideal candidates have a strong background in ASIC design and verification with expertise in SystemVerilog, C/C++, and UVM. Familiarity with constrained random testing, assertion-based verification, and simulation tools like VCS and IES is essential. Knowledge of memory subsystem micro-architecture, cache policies, and interconnects is highly valued. Join our GPU Verification team to drive innovation in High Performance Computing, Graphics, and AI.

What you'll do

  • Define verification scope and develop infrastructure including testbenches, BFMs, checkers, and monitors.
  • Implement comprehensive test plans and coverage strategies to ensure design correctness.
  • Plan and work on strategic direction for advanced verification methodologies.
  • Collaborate with architects and designers to verify complex memory management unit designs.
  • Utilize SystemVerilog, C/C++, and UVM for creating reusable verification components.

What we're looking for

  • 5+ years of relevant work or research experience in ASIC verification
  • Strong proficiency in SystemVerilog, C/C++, test planning, coverage closure
  • Knowledge of constrained random testing and assertion-based verification
  • Experience with simulation tools like VCS and debug tools like Debussy/GDB
  • Understanding of memory subsystem micro-architecture and cache policies
  • Familiarity with UVM, SystemVerilog checkers, scoreboards, and SFV
  • Bachelor’s or Master’s degree in EE, CS, CE or equivalent experience

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