Senior ASIC Verification Engineer

Nvidia

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Posted: 24 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $216k

$124k most similar roles pay here $280k

This role pays more than 80% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

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As a Senior Verification Engineer at NVIDIA, you will join a dynamic team dedicated to advancing consumer graphics, autonomous vehicles, and AI technologies by ensuring the integrity of our leading SoCs and GPUs. Your responsibilities include verifying ASIC designs using UVM methodologies, collaborating with architects and designers to drive comprehensive coverage, and innovating with AI-driven workflows to enhance testbench generation and debug productivity. You will need a strong background in electrical or computer engineering, 8+ years of experience in ASIC verification at both IP and SoC levels, expertise in C/C++, Python scripting, and deep knowledge of low-speed IOs, AXI/APB interconnects, and memory controllers. This role demands proficiency in assertion-based design checks, formal test plan documentation, and a forward-thinking approach to leveraging AI tools for engineering tasks.

Skills

UVM C/C++ Python Perl TCL SVA AXI APB DMA Memory Controllers QSPI UART I2C ASIC verification SoC verification UVM testbenches Constrained random methodology Assertion-based design checks Code coverage Functional coverage Formal test plan documentation AI tools

What you'll do

Lead the verification of ASIC design using UVM methodologies.
Define verification scope and develop robust infrastructure for complex logic.
Collaborate with architects and designers to drive comprehensive coverage.
Innovate by integrating AI-driven workflows into the verification cycle.
Develop architectural golden models and co-verification tests in C/C++.

What we're looking for

8+ years of experience in ASIC verification at both IP and SoC levels.
Proven expertise in building UVM testbenches and applying constrained random methodology.
High proficiency in C/C++ for developing architectural golden models and co-verification tests.
Deep knowledge in Low-Speed IOs, AXI/APB interconnects, DMA controllers, and Memory Controllers.
Expert skills in assertion-based design checks (SVA), code coverage, functional coverage, and formal test plan documentation.
Strong debugging and analytical skills for resolving complex SoC-level issues.
Professional scripting abilities in Python, Perl, or TCL for automation tasks.

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