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Active Keyword: ASIC Implementation Engineer Remove filter Clear all

6 of up to 20 (filtered)

ASIC Design Engineer, IP Integration & Implementation

Apple Inc

Sunnyvale, CA 22 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Above market
RTL ASIC Design AMBA AXI AHB APB UPF Python Perl TCL Logic Synthesis Static Timing Analysis Formal Verification Floorplanning Timing Closure Low-Power Design
3+ yrs exp
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ASIC Design Engineer, IP Integration & Implementation

Apple Inc

Sunnyvale, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL ASIC Design AMBA AXI AHB APB UPF Python Perl TCL Logic Synthesis Static Timing Analysis Formal Verification Floorplanning Timing Closure Low-Power Design FPGA
10+ yrs exp
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ASIC Implementation Engineer PD

Broadcom

San Jose, CA 57 days ago $121,900–$195,000
Actively hiring Confirmed live 2 days ago High trust Below market
Physical Design Floorplanning DRC LVS EMIR Python Tcl Perl EDA Tools Switch Fabric DDR SerDes HBM Chiplet Power Grid Design Multi-voltage Domain
8+ yrs exp
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ASIC Implementation Engineer STA

Broadcom

San Jose, CA 57 days ago $143,800–$230,000
Actively hiring Confirmed live 2 days ago High trust Competitive pay
STA SDC Tcl Python Perl Shell ASIC MMMC Cadence Synopsys Signal Integrity IR-drop DFT PVT ATPG MBIST
10+ yrs exp
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ASIC Implementation Engineer

Broadcom

San Jose, CA 81 days ago $143,800–$230,000
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
Physical Design Floorplanning DRC LVS EMIR Python Tcl Perl EDA Tools High Speed DDR SerDes HBM D2D I/O Chiplet Power Grid Design Multi-voltage Domain Bump Planning
10+ yrs exp
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ASIC Implementation Engineer

Broadcom

San Jose, CA 137 days ago $120,000–$192,000
Actively hiring Confirmed live yesterday Low trust Below market
Physical Design STA Floorplanning Layout Clock Tree Synthesis EM/IR Analysis TCL Perl EDA Tools RTL Tape-out
8+ yrs exp
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