ASIC Engineer

Cisco

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$167,700–$245,200 / yr
Employment
Full-time
Posted
3 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $190k
This role $206k
$134k $257k
below market most similar roles pay here above market

This role pays more than 61% of similar roles. Most pay $162,000–$218,075 — the blue band above. At the midpoint, this role pays about $206k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 272 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 202 roles with salary data.

Most-posted roles

View all roles at Cisco

At a glance

TL;DR · ASIC Engineer

Role Posting Log in to save

The ASIC Engineer joins the Cisco Silicon One team to design, develop, and test complex high-performance silicon for hyperscale infrastructure. This role involves taking end-to-end front-end ownership of ASIC subsystems, where you will define specifications, lead technical reviews, and drive execution across architecture, design, verification, and physical implementation teams. You will design and implement high-frequency RTL using Verilog and SystemVerilog while meeting aggressive timing, power, and area targets. Key responsibilities include performing root-cause analysis during simulation and post-silicon validation, mentoring engineers, and creating reusable code. The role requires expertise in ASIC development flows, including synthesis and static timing analysis, to solve challenges in high-performance silicon. You will work on advanced IC package designs using 2.5D fanout technologies for large-scale integration.

Skills

ASIC Design Verilog SystemVerilog RTL Design Static Timing Analysis Synthesis Simulation Post-Silicon Validation Clock Gating Power Optimization Timing Closure Tape-out IC Package Design 2.5D Fanout

What you'll do

  • Take end-to-end front-end ownership of ASIC subsystems for various Cisco platforms.
  • Design and implement high-frequency, high-performance RTL using Verilog and System Verilog.
  • Meet aggressive timing, power, and area targets for high-performance silicon.
  • Lead design specifications and technical reviews to ensure architectural clarity and high-quality implementation.
  • Drive technical execution across architecture, design, verification, and physical implementation teams.
  • Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.
  • Create reusable code to promote efficiencies in new design developments.
  • Mentor engineers to elevate engineering rigor, design quality, and technical execution.

What we're looking for

  • Bachelor's degree in Electrical or Computer Engineering and 7+ years of ASIC design experience.
  • Master's degree in Electrical or Computer Engineering and 4+ years of ASIC design experience.
  • Experience delivering silicon from microarchitecture, specification, and RTL coding through tape-out at advanced technology nodes.
  • Experience in high-performance RTL design using Verilog and SystemVerilog.
  • Understanding of timing closure, power optimization, and clock gating techniques.
  • Experience with ASIC development flows including simulation, synthesis, and static timing analysis.
  • Experience in documentation, problem-solving, and technical communication skills (preferred).
  • Experience working cross-functionally and collaborating with various technical teams (preferred).

Related searches

More ASIC Engineer jobs ASIC Engineer jobs in San Jose All jobs at Cisco

More like this

Similar roles

ASIC DFT Technical Leader

Cisco

San Jose, CA +1 12 days ago $186,900–$267,700
DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation ATE P1687 RTL Physical Design
10+ yrs exp Hybrid
Save

ASIC Design Engineer

Apple Inc

Santa Clara, CA 43 days ago $129,300–$194,700
ASIC Design RTL Micro-architecture SoC DRAM DFI PHY Memory Subsystem Simulators System-on-a-Chip Architecture Research
Save

ASIC Design Engineer

Apple Inc

Santa Clara, CA 168 days ago $129,300–$194,700
ASIC Design RTL Micro-architecture SoC DRAM DFI PHY Memory Subsystem Simulators System-on-a-Chip Architecture Research
Save

ASIC Design Engineer

Nvidia

Santa Clara, CA 75 days ago
RTL Design Verilog Microarchitecture Logic Synthesis Timing Analysis Python Perl C/C++ VLSI Design Digital Systems Computer Architecture ASIC Design SoC Post-Silicon Validation Front-end Flow
2+ yrs exp
Save

ASIC Design Engineer

Apple Inc

Cupertino, CA 86 days ago $150,400–$277,600
ASIC Design SoC Design Logic Design Lint CDC Synthesis ECO STA Physical Design Power Management Clock Management Python Perl TCL Microarchitecture IP Integration
3+ yrs exp
Save

ASIC Design Engineer

Apple Inc

Cupertino, CA 86 days ago $184,700–$324,800
ASIC Design SoC Design Logic Design Lint CDC Synthesis ECO STA Physical Design Power Management Clock Management Python Perl TCL Microarchitecture IP Integration
10+ yrs exp
Save