ASIC Design Engineer

Nvidia

Confirmed live today High trust
Closes in 6 days

Quick summary

Work type
On-site
Location
Santa Clara, CA
Employment
Full-time
Posted
22 days ago
Freshness
Confirmed live today
Closes
Oct 8, 2026 (soon)
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $185k
$135k most similar roles pay here $227k

This listing doesn't post a salary. Most similar roles pay $152,875–$217,500.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1150 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 912 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer

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As an ASIC Design Engineer - New College Grad 2026, you will join the Memory Subsystem Team to develop sophisticated solutions for SOC interconnects, ordering controllers, and memory accelerators. You will collaborate with architects, design verification, formal verification, and physical design teams to address complex requirements involving area, latency, power, bandwidth, and quality-of-service. Your daily responsibilities include managing micro-architecture and design tasks such as RTL design, synthesis, and timing analysis using innovative CAD tools and the latest process technologies. The role requires proficiency in Verilog or VHDL and scripting languages like PERL. Preferred experience includes high-speed coherent interconnects, protocol bridges, hardware-managed coherency, system level caches, multiple clock domains, asynchronous interfaces, and knowledge of industry specifications such as CHI, CXL, and PCI-E to solve intricate memory subsystem challenges within the hardware architecture.

What does a ASIC Design Engineer earn in California?

Median $214000 from 45 postings across 7 companies.

See salary data

Skills

Verilog VHDL RTL Design Synthesis Timing Analysis ASIC Design PCI-E CXL CHI Perl Micro-architecture CAD Tools Memory Subsystem System Level Caches Clock Domains

What you'll do

  • Design micro-architecture and RTL for memory subsystems including interconnects and controllers.
  • Perform synthesis and timing analysis using advanced CAD tools and process technologies.
  • Develop solutions that meet complex area, latency, power, bandwidth, and quality-of-service requirements.
  • Implement high-speed coherent interconnects and protocol bridges.
  • Manage hardware-managed coherency and system level caches.
  • Handle multiple clock domains and asynchronous interfaces.
  • Utilize Verilog or VHDL for hardware design and scripting languages like PERL for automation.

What we're looking for

  • Pursuing or recently completed a BS or MS in Electrical Engineering, Computer Engineering, or a related degree.
  • Strong proficiency in Verilog or VHDL.
  • Proficiency in a scripting language like PERL.
  • Exposure to high-speed coherent interconnects, protocol bridges, hardware-managed coherency, and system level caches (preferred).
  • Experience with multiple clock domains and asynchronous interfaces (preferred).
  • Knowledge of industry specifications such as CHI, CXL, or PCIe (preferred).

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