ASIC Design Engineer, Neural Engine DMA

What you'll do

• Design DMA subsystem blocks from microarchitecture specification through tapeout.
• Write well-parameterized RTL structured for correct synthesis, clean timing, and low power.
• Implement assertions and cover points to encode design intent and ensure verification completeness.
• Execute front-end implementation tasks including synthesis, timing closure, area/power analysis, and linting.
• Perform logic equivalence checks during the front-end design cycle.
• Contribute to micro-architectural specifications to meet performance, power, and area targets.
• Review test plans and debug failures in coordination with verification teams.
• Ensure the design's intended behavior is fully exercised through formal and functional verification.

What we're looking for

• Bachelor's degree required.
• Familiarity with Verilog or SystemVerilog and core digital design fundamentals like FSMs, pipelining, and timing.
• Exposure to on-chip bus protocols such as AMBA (AXI, AHB, APB).
• Knowledge of system-level concepts including SoC data movement, flow control, and memory system trade-offs.
• Background or interest in high-bandwidth domains like networking, multimedia, or AI/ML.
• Familiarity with scripting languages such as Python, Perl, or Tcl for design automation.
• Strong technical writing skills and the ability to contribute constructively in design reviews.