Physical IC Design Engineer

Broadcom

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
San Jose, CA
Posted
32 days ago
Freshness
Confirmed live yesterday
Closes
Feb 6, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $192k
$141k most similar roles pay here $240k

This listing doesn't post a salary. Most similar roles pay $162,000–$222,250.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Physical IC Design Engineer

Role Posting Log in to save

The Physical IC Design Engineer joins the Asic Products Division to support the development of PCIe Switch Products for Artificial Intelligence, Machine Learning ecosystems, and Enterprise Storage Products. This role involves managing the full physical design cycle from RTL to silicon tape-out. Key responsibilities include executing synthesis, physical verification, and timing closure through various strategies, alongside performing EM/IR analysis, place and route, clock tree synthesis, floor-planning, and layout flow methodology development. The successful candidate will collaborate with IC Design RTL Engineers to solve complex hardware challenges. Required technical skills include proficiency in TCL and PERL scripting along with expertise in related EDA tools. Candidates must possess a Bachelor’s degree in Electrical Engineering or Electronics Engineering and have over twelve years of relevant experience in the physical design cycle for high-performance semiconductor products.

Skills

Physical Design RTL to Tape-out Synthesis Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools ASIC PCIe Machine Learning

What you'll do

  • Execute the full physical design cycle from RTL to silicon tape-out.
  • Perform synthesis, physical verification, and timing closure using various methods and strategies.
  • Conduct EM/IR analysis for integrated circuit designs.
  • Manage place and route processes and clock tree synthesis.
  • Develop floor-planning, layout flows, and overall methodology.
  • Utilize TCL and PERL scripting to automate tasks within EDA tools.

What we're looking for

  • Bachelor's degree in Electrical Engineering or Electronics Engineering.
  • 12+ years of relevant experience.
  • Expertise in all Physical Design aspects from RTL to silicon tape-out.
  • Proficiency in TCL and PERL scripting.
  • Proficiency in related EDA tools.
  • Experience with Synthesis, Physical Verification, and Timing Closure.
  • Experience with EM/IR Analysis, Place and Route, Clock Tree Synthesis, and Floor-planning.
  • Excellent verbal and written communication skills.

Related searches

More Physical IC Design Engineer jobs Physical IC Design Engineer jobs in San Jose All jobs at Broadcom

More like this

Similar roles

Physical IC Design Engineer

Broadcom

San Jose, CA 84 days ago $143,800–$230,000
Physical Design RTL to Tape-out Synthesis Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools ASIC Machine Learning PCIe
10+ yrs exp
Save

Physical Design Engineer

Broadcom

San Jose, CA 18 days ago $143,800–$230,000
ASIC Physical Layout 3D IC DRC LVS TCL Python SI PI RDL Advanced Packaging PCB
10+ yrs exp
Save

Physical Design Engineer

Broadcom

San Jose, CA 18 days ago $143,800–$230,000
ASIC Physical Layout 3D IC DRC LVS TCL Python High-Speed Signal Interconnects SI PI RDL Advanced Packaging PCB Layout
10+ yrs exp
Save

Principal IC Design Engineer

Broadcom

Broomfield, CO +1 2 days ago $129,400–$207,000
Verilog VHDL SystemVerilog SOC Architecture DRAM Interface Design Synthesis Formal Verification Timing Closure Signal Integrity Physical Implementation HDL
10+ yrs exp
Save

Physical Design Engineer II, Silicon Engineering

SpaceX

Austin, TX 133 days ago
ASIC Physical Design RTL2GDSII Static Timing Analysis STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Synthesis
3+ yrs exp
Save

Physical Design Engineer II, Silicon Engineering

SpaceX

Irvine, CA 150 days ago $145,000–$195,000
ASIC RTL2GDSII Physical Design STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Synthesis
3+ yrs exp
Save