Physical IC Design Engineer

Broadcom

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
San Jose, CA
Employment
Full-time
Posted
78 days ago
Freshness
Confirmed live yesterday
Closes
Feb 6, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $205k
$137k $273k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $168,200–$241,750.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Physical IC Design Engineer

Role Posting Log in to save

Broadcom is seeking a Physical IC Design Engineer to join the Asic Products Division. This role involves managing the full physical design cycle from RTL to silicon tape-out for PCIe Switch Products and Enterprise Storage Products. The engineer will be responsible for executing synthesis, physical verification, and timing closure while performing floor-planning, layout, and clock tree synthesis. Key tasks include EM/IR analysis, flow and methodology development, and collaborating with IC Design RTL Engineers. Candidates must possess a Bachelor’s degree in Electrical Engineering or Electronics Engineering and over 12 years of relevant experience. Required technical skills include proficiency in related EDA tools and TCL/PERL scripting. The position focuses on driving performance for Artificial Intelligence and Machine Learning ecosystems and managing mega datacenters.

Skills

Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools Flow and Methodology Development

What you'll do

  • Execute the full physical design cycle from RTL to silicon tape-out.
  • Perform synthesis, physical verification, and timing closure using various strategies.
  • Conduct floor-planning and layout for integrated circuits.
  • Perform Place and Route and Clock Tree Synthesis.
  • Conduct EM/IR analysis to ensure power integrity.
  • Develop internal flows and methodologies for the design process.
  • Set up and synthesize RTL designs.

What we're looking for

  • Bachelor’s degree in Electrical Engineering or Electronics Engineering.
  • 12+ years of relevant experience.
  • Full physical design cycle experience from RTL to tape-out.
  • Proficiency in related EDA tools.
  • TCL/PERL scripting skills.
  • Expertise in Synthesis, Physical Verification, and Timing Closure.
  • Experience in EM/IR Analysis, Place and Route, Clock Tree Synthesis, and Floor-planning.
  • Excellent verbal and written communication skills.

Related searches

More Physical IC Design Engineer jobs Physical IC Design Engineer jobs in San Jose All jobs at Broadcom

More like this

Similar roles

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 29 days ago $121,900–$195,000
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools RTL
8+ yrs exp
Save

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 29 days ago $121,900–$195,000
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design
8+ yrs exp
Save

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 29 days ago $129,400–$207,000
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools RTL
10+ yrs exp
Save

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 60 days ago $129,400–$207,000
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design
10+ yrs exp
Save

Physical Design Engineer

Broadcom

San Jose, CA +1 18 days ago
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design
10+ yrs exp
Save

Physical Design Engineer

SpaceX

Irvine, CA +2 46 days ago $125,000–$160,000
ASIC Design RTL2GDSII Physical Design Static Timing Analysis STA Floorplanning Place and Route Physical Verification Electromigration Voltage Drop Logic Equivalency FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools
1+ yrs exp
Save