Packaging Substrate Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $184,700–$324,800 / yr
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $209k

This role $255k

$140k $345k

below market most similar roles pay here above market

This role pays more than 91% of similar roles. Most pay $177,237–$241,750 — the blue band above. At the midpoint, this role pays about $255k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3515 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2718 roles with salary data.

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At a glance

TL;DR · Packaging Substrate Engineer

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The Packaging Substrate Engineer joins the Hardware Technology Packaging team to invent, design, and integrate electronic packaging solutions for internal and custom external components of consumer electronic products. This role involves owning sophisticated package selection, new-generation package structure optimization, and roadmap definition for package substrates. Key responsibilities include leading SoC package substrate technology development, pathfinding, and working with industry partners, foundries, and OSATs to move solutions from concept to high-volume manufacturing. The position requires expertise in material, chemistry, and mechanical engineering, specifically regarding Cu plating, lithography, dielectric materials, via formation, solder resist, and surface finish. Candidates must possess in-depth knowledge of substrate manufacturing processes, design rules, and the Cadence Allegro platform for design review for manufacturing to solve technical issues throughout the product development cycle.

Skills

Substrate Technology Cu Plating Lithography Via Formation Solder Resist Surface Finish Cadence Allegro DFM Package Assembly Mechanical Engineering Chemistry HVM

What you'll do

Lead SoC package substrate technology development, pathfinding, and roadmap definition.
Develop new substrate technologies from initial concept to high-volume manufacturing (HVM).
Optimize new package substrate architectures based on performance, technical risk, cost, and availability.
Drive development of new package architectures, materials, processes, and specification definitions.
Solve technical issues occurring during the full product development cycle.
Manage relationships with substrate manufacturing partners, foundries, and OSAT providers.

What we're looking for

BS and 10+ years of relevant industry experience.
MS or Ph.D. and 8+ years of relevant industry experience (preferred).
Proven fundamentals in material, chemistry, or mechanical engineering field(s) (preferred).
In-depth knowledge of substrate technology, manufacturing process, design rules, and roadmap (preferred).
Hands-on experience in substrate manufacturing and technology development including Cu plating, lithography, and dielectric materials (preferred).
Experience in Cadence Allegro platform tools and design review for manufacturing (preferred).
Exceptional technology development and project management skills (preferred).
Strong communication and collaborative skills (preferred).

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