below marketmost similar roles pay hereabove market
This role pays less than
88%
of similar roles. Most pay
$162,000–$214,250
— the blue band above.
At the midpoint, this role pays about
$143k
versus about
$188k
for comparable roles.
Based on 240 similar postings.
Employer
About General Dynamics
General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.
General Dynamics currently has
1351 open roles
on FindRole.
Listed pay typically runs
$124,093–$150,385
across 1176 roles with salary data.
The Advanced ASIC FPGA Verification Engineer joins the engineering team to lead the development and maintenance of UVM-based and non-UVM-based verification environments for complex FPGA designs. This role involves creating comprehensive verification plans, implementing constrained-random stimulus generators, monitors, and scoreboards, and driving code and functional coverage to closure. You will build and improve CI/CD pipelines using Jenkins or GitLab CI, perform assertion-based verification using SystemVerilog Assertions, and debug design issues via waveform analysis in QuestaSim or Vivado. Key technical requirements include proficiency in SystemVerilog, VHDL, and UVM, alongside knowledge of AXI-Stream and AXI4 protocols. The work focuses on verifying cryptographic engines, protocol interfaces, and system-level integration testbenches, ensuring design observability and reliability for mission-critical hardware implementations.
Develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs.
Create comprehensive verification plans including functional coverage models, goals, and closure criteria.
Implement constrained-random stimulus generators, monitors, scoreboards, and functional coverage collectors using SystemVerilog and VHDL.
Drive code and functional coverage to closure by analyzing coverage holes and developing targeted stimulus.
Build and improve CI/CD pipelines for automated verification workflows and nightly regression runs.
Perform assertion-based verification using SystemVerilog Assertions to capture protocol rules and design invariants.
Debug complex design issues using waveform analysis, assertion failures, and coverage-driven investigation.
Support formal verification activities including property checking, connectivity verification, and equivalence checking.
What we're looking for
Bachelor's degree in Electrical or Computer Engineering, or a related field, plus 5 years of experience; or a Master's degree plus 3 years of experience.
U.S. citizenship is required.
Department of Defense Secret security clearance is required at time of hire.
Strong proficiency in SystemVerilog and VHDL for verification, including constrained-random stimulus, functional coverage, and assertions.
Hands-on experience with UVM environment architecture, component development, and sequence libraries.
Experience with industry-standard simulation tools like QuestaSim/ModelSim and waveform debugging.
Experience with code coverage metrics, verification plans, and coverage-driven closure.
Understanding of AXI-Stream, AXI4, and clock domain crossing (CDC) verification concepts.