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Perl Python Tcl Make SPICE Liberty models Deep Learning GPU Parallel Computing CI/CD +5 more Show less

Cadence_Virtuoso Python Linux Verilog SystemVerilog Analog-to-Digital_Converters Digital-to-Analog_Converters Phase-Locked_Loops RF_Components Cryogenic_Circuit_Design Low_Temperature_Measurements Semiconductor_Behavior ASIC_Bring-Up Characterization Signal_Integrity Documentation +11 more Show less

Spice Perl Tcl Make RTL Logic Synthesis Verification Place and Route Design-for-test(DFT) Analog Circuit Design Mixed-Signal Analog Block Design Digital Circuit Design Security Attacks Detection Circuits EM/IR Analysis Static Timing Analysis Noise Analysis Loop Stability Analysis Monte-Carlo Analysis +13 more Show less

Perl Python Verilog VHDL SPICE Tcl Make RTL Simulation tools Waveform debugging tools ASIC design flow Custom circuit design SRAM design Transistor-level circuit design Power analysis Timing characterization Circuit verification Scripting languages Automation methods +14 more Show less

Spice Python Perl Tcl Make RTL Logic Synthesis Verification Auto Place and Route STA PnR DRC LVS Power Gating Multi-Vt Post-Silicon Characterization Custom Circuit Design Semi-Custom Circuit Design +13 more Show less