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RF Analog Design Mixed-Signal Engineering Internship

Qualcomm

San Diego, CA +12 7 days ago
Actively hiring Confirmed live yesterday Posted this week High trust
RF Analog IC Design Mixed-Signal Design RFIC Cadence HFSS MATLAB Perl Python Verilog SystemVerilog Tcl Shell RTL DFT SerDes PCIe USB DDR HBM SIPI PDN

RF/Analog Mixed Signal Design Engineer

Apple Inc

Sunnyvale, CA 8 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
Analog IC Design Mixed-Signal Design VerilogA Python Matlab C ASIC Spectrum Analyzers Oscilloscopes PLLs LDOs ESD Compliance
10+ yrs exp

Analog/Mixed Signal ASIC Design Engineer

Qualcomm

San Diego, CA 8 days ago $101,400–$152,200
Actively hiring Confirmed live yesterday High trust Below market
CMOS Mixed Signal Design Cadence ADE MATLAB SPICE Verilog VHDL PLL SERDES 5G Analog Design Automation Layout Silicon Evaluation
2+ yrs exp

Analog/Mixed Signal ASIC Design Engineer

Qualcomm

San Diego, CA 8 days ago $145,600–$218,400
Actively hiring Confirmed live yesterday High trust Competitive pay
Cadence Virtuoso ASIC Design SerDes DDR PLL DAC ADC Python MATLAB SPICE Verilog VHDL Circuit Simulation Schematic Capture FinFET CMOS
2+ yrs exp

Analog Mixed Signal Power Management Design Engineer

Qualcomm

San Diego, CA 8 days ago $145,600–$218,400
Actively hiring Confirmed live yesterday High trust Competitive pay
Mixed-Signal IC Design CMOS FinFET Cadence SPICE MATLAB Verilog VHDL ASIC Layout Data Converters PLL Analog Design Automation ATE Verification
5+ yrs exp

Analog/Mixed Signal ASIC Design Engineer

Qualcomm

San Diego, CA 8 days ago $145,600–$218,400
Actively hiring Confirmed live yesterday High trust Competitive pay
Cadence Virtuoso ASIC Design SerDes PLL DAC ADC Matlab Python SPICE Verilog VHDL CMOS FinFET Signal Processing Schematic Capture
2+ yrs exp

Senior Digital / Mixed-Signal IC Design or Verification Engineer

Broadcom

Mendota Heights, MN +1 17 days ago $109,700–$175,500
Actively hiring Confirmed live yesterday High trust Below market
UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting
8+ yrs exp