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UVM SystemVerilog Verilog C C++ RTL GPU Architecture SystemC TLM Linux Perl Ruby Shell Scripting Makefiles ASIC Design Verification Simulation High-Level Synthesis +12 more Show less

C C++ CUDA Python Perl Shell Linux Git Perforce JIRA Confluence Make Compiler Verification High-Performance Computing SDLC Test Automation Statistical Analysis +12 more Show less

SystemVerilog C++ Python GPU Architecture RTL Constrained-Random Testing Functional Coverage Computer Architecture Graphics Pipelines 3D Graphics Verification Testbenches Semiconductor Design +7 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification RTL Constrained-Random Testing Functional Coverage Computer Architecture Hardware Modeling Emulation Performance Profiling Coherent Interconnects +9 more Show less

Formal Verification SystemVerilog SVA Python C/C++ Perl UVM EDA Tools RTL Computer Architecture Graphics Pipelines Power Gating UPF JIRA Confluence Memory Subsystems +11 more Show less

ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics +12 more Show less

UVM C++ C Python Perl ASIC Design Computer Architecture Memory Models VCS Emulation FPGA Post-silicon Verification +7 more Show less

ASIC Verification C++ C Python Perl VCS Emulation FPGA Computer Architecture Memory Models Post-silicon Verification Debug Tools +7 more Show less

UVM System Verilog C C++ VCS Verdi GDB ASIC Verification Functional Coverage Assertion-Based Verification Random Stimulus post silicon verification GPU +8 more Show less

GPU Architecture RTL Emulation SystemC Python C++ Linux OpenGL Vulkan OpenCL Performance Modeling Profiling Automation AI/ML SoC Sparta +11 more Show less

GPU Architecture C++ Python Linux RTL Emulation SystemC OpenGL Vulkan OpenCL Performance Modeling AI/ML Sparta SoC Design Profiling Tools Automation Frameworks +11 more Show less

SystemVerilog UVM ASIC Verification RTL Computer Architecture Assertion-based Verification object oriented programming Coverage Closure test bench design Post-silicon Validation Semiformal Verification AI +7 more Show less

ASIC Verification C++ Python Perl VCS Emulation FPGA Computer Architecture Memory Models Post-silicon Verification Debug Tools +6 more Show less

System Verilog Verilog UVM Python C++ ASIC Verification Pre-silicon Testbench Development Computer Architecture Arbitration Scripting Data Structures Algorithms RTL Performance Verification +10 more Show less

UVM System Verilog VCS Verdi Indago GDB C C++ Perl Assertion-based Verification Functional Coverage Random Stimulus ASIC Verification Post-silicon Verification +9 more Show less

System Verilog UVM Verilog VHDL C C++ Python Vulkan FPGA Emulation Palladium Zebu QEMU Make Airflow GDB uboot UEFI +13 more Show less