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ASIC Design Engineer - Cache Controller

Apple Inc

Santa Clara, CA 53 days ago $181,100–$318,400

Actively hiring Verified listing Above market

RTL Cache PPA ASIC Memory_Systems Multi_Processor_Coherence_Protocols DRAM_Controller SoC Register_Transfer_Level Front_End_Netlist_Analysis Physical_Design_Timing_Closure

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ASIC Design Engineer - Cache Controller

Apple Inc

Santa Clara, CA 53 days ago $147,400–$272,100

Actively hiring Verified listing Above market

RTL Verilog SystemVerilog Cache Coherence Protocols DRAM Controller PPA Analysis SoC Design ASIC Design Memory Systems High Performance Computing Mentor Graphics Calibre Synopsys DC Compiler Tensilica Diamond Standard Library

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Senior Logic Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 87 days ago $136,000–$218,500

Actively hiring Verified listing Competitive pay

Verilog RTL ASIC Logic Synthesis DFT Timing Analysis Floor-planning ECO Cache Coherency High Speed Interconnects Computer Architecture

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