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Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 32 days ago $136,000–$218,500
Actively hiring Confirmed live 2 days ago High trust Competitive pay
Physical Design Synthesis Timing Analysis Floor-planning Verilog ASIC Design Flow RTL Design Verification DFT ECO High-frequency Design Micro-architecture
5+ yrs exp
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ASIC Design Engineer, Cache Controller

Apple Inc

Santa Clara, CA 144 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago High trust Above market
ASIC Design RTL Micro-architecture SoC Cache Coherence Protocols DRAM Controller Timing Closure Memory Systems Interconnect Architectures
10+ yrs exp
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ASIC Design Engineer, Cache Controller

Apple Inc

Santa Clara, CA 144 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday High trust Above market
ASIC Design RTL Micro-architecture SoC Cache Coherence DRAM Controller Timing Closure Netlist Memory Systems Interconnect Architectures
3+ yrs exp
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Senior Logic Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 177 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Trusted Competitive pay
Verilog RTL ASIC Design Flow Logic Synthesis Timing Closure Computer Architecture Cache Coherency high speed interconnects DFT Floor-planning ECO Lab Debug
5+ yrs exp Hybrid
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