Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: CPU RTL Design Engineer Remove filter Clear all

7 of up to 20 (filtered)

CPU RTL Design Engineer

Amd

Austin, TX 4 days ago $121,680–$182,520
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Static Timing Analysis Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Timing Closure
Save

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 9 days ago $175,600–$263,400
Actively hiring Confirmed live today Trusted Competitive pay
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution
4+ yrs exp
Save

Director, CPU RTL Design Engineering

Amd

Remote (Santa Clara, CA) 15 days ago $248,800–$373,200
Actively hiring Confirmed live today High trust Above market
RTL Design x86 Computer Architecture Processor Pipeline Memory Hierarchy Instruction Set Architecture Logic Design Python Ruby Perl Silicon Development Lifecycle Tapeout Scripting Automation
Remote
Save

CPU Microarchitecture & Cache RTL Design Engineer

Amd

Fort Collins, CO 18 days ago $144,800–$217,200
Actively hiring Confirmed live today High trust Below market
VLSI RTL Design Verilog HDL Cache Architecture CPU Coherency NoC SoC Scripting Microarchitecture Timing Closure Design for Test Physical Design Routing Fabric
Save

Next Gen CPU Power Management RTL Design Engineer

Amd

Santa Clara, CA 22 days ago $166,400–$249,600
Actively hiring Confirmed live today High trust Competitive pay
Verilog SystemVerilog C++ C RTL Design Microarchitecture Power Management Clock Domain Crossing CDC Analysis Firmware DVFS Silicon Validation Design-for-Debug Design-for-Test Digital Design
Save

CPU RTL Power, Clocking, Reset Design Engineer

Amd

Fort Collins, CO 26 days ago $144,800–$217,200
Actively hiring Confirmed live today High trust Below market
RTL Design Verilog HDL Microarchitecture clock-domain crossing Power Management Voltage Management Scripting Tapeout Closure Design-for-Test Physical Design Control Fabric
Save

CPU Core RTL Design Engineer

Amd

Austin, TX 94 days ago $178,400–$267,600
Actively hiring Confirmed live today High trust Above market
Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Power Management Post-Silicon Debug SoC Microarchitecture
Save