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Silicon Validation Software Engineer: CPU and Memory Hierarchy

Apple Inc

Cupertino, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Above market
C C++ Python Post-Silicon Validation SoC CPU Microarchitecture Cache Coherency Memory Hierarchy System Bring-up Silicon Debug PVT Scripting Automation
3+ yrs exp

Graphics Cache Hierarchy Design Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog UVM Verilog VHDL RTL Verification Computer Architecture GPU Architecture Cache Verification Memory Management Unit Shell Scripting Perl Ruby Makefiles HDL Simulators Waveform Viewers Functional Coverage SoC
3+ yrs exp

Graphics Cache Hierarchy Design Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Trusted Below market
SystemVerilog Verilog RTL Verification Computer Architecture GPU Architecture Object Oriented Programming Data Structures Perl Ruby Shell Scripting Makefiles HDL Simulators Waveform Viewers Caches Memory Management Unit Interconnects

GPU Design Engineer, Memory Hierarchy

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Above market
Verilog System Verilog HDL Python Perl Ruby GPU Architecture SoC RTL Coding Cache On-chip Interconnect Data Compression Power Optimization Functional Simulation Debug
3+ yrs exp

GPU Design Engineer, Memory Hierarchy

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
GPU Architecture Micro-architecture Verilog System Verilog HDL RTL C++ Python Perl Ruby SoC Cache Memory Subsystem On-chip Interconnect Data Compression Architectural Modeling
10+ yrs exp

Graphics Cache Hierarchy Design Verification Engineer

Apple Inc

Santa Clara, CA 91 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Low trust Competitive pay
SystemVerilog UVM Verilog VHDL RTL Verification Computer Architecture GPU Architecture Cache Verification Memory Management Unit Shell Scripting Perl Ruby Makefiles HDL Simulators Waveform Viewers Functional Coverage
2+ yrs exp