Silicon Validation Software Engineer: CPU and Memory Hierarchy

As a Silicon Validation Software Engineer: CPU and Memory Hierarchy, you will join a team of experienced software engineers and debuggers to validate world-class silicon. You will write functional validation software for CPUs, caches, and memory subsystems within SoCs to identify logic design and circuit bugs before product release. Your daily responsibilities include developing targeted stress tests to expose incorrect behavior under varying voltage, frequency, and temperature conditions while analyzing logs, counters, and traces to understand system behavior. You will collaborate with SoC design and product engineering teams to root-cause issues and provide feedback on operating limits. The role requires proficiency in C, C++, and Python for automation and analysis. You must possess a strong understanding of CPU microarchitecture, cache coherency, memory hierarchy, and SoC-level power, clocking, and voltage domains.