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Incisive Low-Power Synopsys VCS NLP Verdi Verilog SystemVerilog UVM Python Perl C C++ UPF Makefile +7 more Show less

SystemVerilog VLSI RTL HDL Physical Design Computer Architecture AI GPU Deep Learning CI/CD +4 more Show less

Verilog SystemVerilog UVM Incisive Low-Power Synopsys VCS NLP Verdi Python Perl C C++ UPF Makefile +7 more Show less

PTPX Power_Artist UPF Python Shell Perl ASIC low_power_design wireless_communication_SoCs CPU fabric peripherals PCIe +8 more Show less

PTPX Power_Artist UPF Python Shell Perl ASIC low_power_design wireless_communication WIFI BT UWB PCIe problem_solving analytical_skills +10 more Show less

PTPX Power_Artist Python UPF Shell Perl ASIC low_power_design STA Wireless WIFI BT UWB PCIe CPU fabric peripherals +12 more Show less

PTPX Power_Artist Python UPF Shell Perl CPU PCIe Wireless WIFI BT UWB ASIC_PD STA +9 more Show less

Python Verilog C++ UPF DVFS multi-VT clock gating power gating voltage islands Power Estimation SW-driven power virus tests silicon debug Power Supply Analysis Oscilloscopes DAQs +10 more Show less