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ASIC Physical Design Static Timing Analysis Clock-Tree Synthesis ECO Synopsys ICC2 Fusion Compiler Cadence Innovus PrimeTime RedHawk Formality Conformal TCL Python Perl Pandas Machine Learning PPA Optimization +13 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture +9 more Show less

Physical Design Synthesis Timing Analysis Floor-planning Verilog ASIC Design Flow RTL Design Verification DFT ECO High-frequency Design Micro-architecture +7 more Show less

C++ VLSI Physical Design EDA Tools Machine Learning Graph Neural Networks Python Tcl Perl multithreading Distributed Computing ICC2 Innovus PrimeTime Tempus StarRC +10 more Show less

Physical Design Static Timing Analysis Logic Synthesis Floorplanning Clock-tree Synthesis Routing ECO RTL Python Tcl Perl Make AI Deep Learning LLMs EDA Tools +11 more Show less

C++ VLSI Physical Design Computational Geometry Graph Theory Machine Learning ICC2 Innovus Multithreading Distributed Computing Algorithm Development C++17 C++14 +7 more Show less