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Active Keyword: ASIC Design Engineer Remove filter Location: Palo Alto Remove filter Clear all

7 of up to 20 (filtered)

Senior ASIC Design Engineer

SpaceX

Palo Alto, CA +3 2 days ago $175,000–$280,000
Actively hiring Confirmed live today Posted this week High trust Above market
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp
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ASIC Design Engineer

SpaceX

Palo Alto, CA +2 2 days ago $135,000–$175,000
Actively hiring Confirmed live today Posted this week High trust Below market
ASIC Design FPGA Verilog SystemVerilog VHDL RTL Design Python C/C++ Bash SoC Integration DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer
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Senior ASIC Design Engineer

SpaceX

Irvine, CA +3 11 days ago $165,000–$265,000
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog System Verilog RTL Design ASIC SoC Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp
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Senior ASIC Design Engineer

SpaceX

Redmond, WA +3 11 days ago $165,000–$270,000
Actively hiring Confirmed live today High trust Above market
RTL Design Verilog System Verilog ASIC SoC Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems
5+ yrs exp
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Senior ASIC Design Engineer

SpaceX

Austin, TX +3 11 days ago
Actively hiring Confirmed live today Trusted
Verilog System Verilog RTL Design ASIC SoC Synthesis Timing Closure AXI AHB Python HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems Formality Check Silicon Bring-up
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Palo Alto, CA 89 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Palo Alto, CA +3 138 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
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