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FPGA VHDL Verilog DSP Digital Signal Processing HLS ModelSim Synplicity Xilinx Vivado Altera Quartus Matlab SystemC C C++ Git Bitbucket JIRA Ethernet PCIe UART SPI +16 more Show less

Electrical Engineering Link 16 FPGA Configuration Management Hardware Design Technical Data Packages Risk Mitigation Integration +3 more Show less

FPGA VHDL Verilog DSP Digital Signal Processing HLS ModelSim Synplicity Xilinx Vivado Altera Quartus Matlab SystemC C C++ Git Bitbucket JIRA Ethernet PCIe SDRAM DDR3 JESD UART SPI +19 more Show less

Design-for-Manufacturing (DFM Statistical Process Control (SPC) Six Sigma Python Machine Learning JMP Spotfire Silicon Photonics Wafer Sort Advanced Packaging DFT Root-Cause Analysis +7 more Show less

ASIC DFT System Verilog Tcl Python Perl JTAG Scan BIST ATPG TestMax Tetramax Tessent PrimeTime Verilog RTL Logic Equivalency Checking +12 more Show less

Mixed-Signal Design Silicon Photonics Cadence Virtuoso Spectre Caliber SystemVerilog Verilog-AMS Python C SerDes PAM4 TIA ADC DAC DFT SI/PI Ethernet UCIE Verilog-A +14 more Show less

Python C/C++ MATLAB IBIS-AMI ADS HSPICE Cadence Linux Perl TCL SerDes PAM4 DSP Ethernet Signal Integrity ASIC SoC +12 more Show less

System Verilog UVM Verilog Python Perl TCL Formal Verification ASIC Design Verification Ethernet UCIE SPI I2C Veloce HAPS SerDes PAM4 +11 more Show less