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Analog Mixed-Signal Design SerDes CMOS FinFET SystemVerilog Matlab Python VerilogAMS PCIe USB MPHY CDR CTLE DFE LDO Primetime Nanotime Scripting +13 more Show less

Analog Mixed-Signal Design SerDes High-Speed Serial Links CMOS FinFET SystemVerilog Matlab Python VerilogAMS CDR PLL LDO PAM NRZ CTLE DFE PCIe USB MPHY Primetime Nanotime Scripting Automation +18 more Show less

SERDES FinFET VerilogA AMS CMOS Spectrum Analyzers Oscilloscopes Signal Generators DLLs LDO Regulators Biasing Circuits Switched-Cap Circuits High-Speed Data Converters +8 more Show less

ASIC PPA Low Power Design SOC Virtuoso DRC LVS DRM Perl TCL PDV Circuit QA Layout IPDK Power Management Cells Level Shifters +11 more Show less

Circuit Design Standard Cell Library PPA Layout Optimization PNR RTL2GDSII Static Timing Analysis STA Process Monitor IP PDK SOC GPU CPU Flip Flops Level Shifters +10 more Show less

Circuit Design Standard Cell Library PPA Layout Optimization PNR RTL2GDSII Static Timing Analysis STA PDK Process Monitor IP Flip Flops Level Shifters Retention Flops SOC GPU CPU +11 more Show less

SRAM Design Circuit Design RTL SoC Design Schematic Capture DFT IR/EM Machine Learning +3 more Show less

SRAM Design Circuit Design RTL SoC Design DFT Schematic Capture IR/EM Machine Learning Simulations Silicon Debug Memory Hierarchy +6 more Show less

ASIC SOC SRAM ML Accelerators Python Perl SPICE Schematic Capture Mixed Signal Verification CAD Automation Silicon Debug ATE DC/DC Converters +8 more Show less