below marketmost similar roles pay hereabove market
This role pays less than
61%
of similar roles. Most pay
$168,500–$241,750
— the blue band above.
At the midpoint, this role pays about
$177k
versus about
$205k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
JOB TITLE: Wireless Design Verification Engineer
The Wireless Design Verification Engineer joins the wireless silicon development team to support the design of highly energy-efficient wireless SoCs. In this role, you will perform pre-silicon RTL verification of the wireless MAC and its interfaces with the rest of the SoC. You will collaborate with DV methodologists, designers, and communication systems engineers to develop reusable testbenches and verification environments using metric-driven verification. Key responsibilities include creating UVM libraries, developing directed and constrained random tests, and managing bug tracking. You will utilize Verilog, SystemVerilog, UVM, SystemVerilog Assertion, Python, and Shell scripting. Additionally, you will use machine learning and AI technologies for data mining and analysis. The work involves validating wireless protocols such as Bluetooth, UWB, WLAN, and Zigbee using Palladium and FPGA.
Create verification plans from specifications to achieve specific coverage targets for the MAC subsystem.
Build block and subsystem level testbenches using UVM libraries and reusable architectures.
Develop and execute directed and constrained random tests to identify and debug design failures.
Manage bug tracking and work with designers to drive the closure of identified issues.
Create and analyze coverage models to identify gaps and add necessary test cases.
Utilize machine learning and AI technologies to identify design and testbench issues.
Support MAC subsystem validation using Palladium and FPGA platforms.
Improve and refine internal design verification methodologies and flows.
What we're looking for
Minimum requirement of a bachelor's degree.
3+ years of verification experience of wireless/wired communication block/subsystem (preferred).
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion (preferred).
Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage (preferred).
Verification experience of MAC, PHY, DMA, timer, AMBA bus and fabric, or encryption/decryption engine (preferred).
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee (preferred).
Proficient in shell, Python, and Perl scripting (preferred).
Experience using AI technologies in data mining/analysis and Palladium/FPGA validation (preferred).