Wireless Design Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $129,300–$225,300 / yr
Posted: 57 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $191k

This role $177k

$118k most similar roles pay here $237k

This role pays more than 54% of similar roles. Most pay $167,925–$214,000 — the shaded band above. At the midpoint, this role pays about $177k versus about $191k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Wireless Design Verification Engineer

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Wireless Design Verification Engineer will join the wireless silicon development team to perform pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. The role involves collaborating with methodologists, designers, and communication systems engineers to develop reusable testbenches and verification environments using metric-driven methodologies. Key responsibilities include creating verification plans from specifications, building UVM libraries, executing directed and constrained random tests, managing bug tracking, and analyzing coverage models. The candidate will utilize Verilog, SystemVerilog, UVM, SystemVerilog Assertions, and scripting in Shell, Python, or Perl. Additionally, the role involves using machine learning for data mining and performing validation on Palladium or FPGA hardware. This position addresses technical challenges in wireless communication subsystems involving protocols such as Bluetooth, UWB, WLAN, or Zigbee within a high-performance silicon environment.

Skills

SystemVerilog UVM Verilog Python Shell Perl Palladium FPGA RTL Verification MAC PHY DMA AMBA Bluetooth WLAN Zigbee UWB Machine Learning AI

What you'll do

Create verification plans from specifications and refine them to achieve coverage targets for the MAC subsystem.
Build block and subsystem level testbenches using UVM libraries and best-in-class DV methodologies.
Develop and execute directed and constrained random tests to identify and debug design failures.
Manage bug tracking and work with designers to drive the closure of identified issues.
Create and analyze coverage models while adding specific test cases to increase overall coverage.
Utilize machine learning and AI technologies to identify design flaws and ensure verification quality.
Support MAC subsystem validation using Palladium and FPGA platforms.
Improve internal DV methodologies and workflows through continuous collaboration with team members.

What we're looking for

A bachelor's degree is required.
3+ years of verification experience with wireless or wired communication blocks/subsystems is preferred.
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion is preferred.
Experience in ASIC verification flows including testbench development, constrained random testing, and coverage analysis is preferred.
Verification experience with MAC, PHY, DMA, timers, AMBA bus/fabric, or encryption engines is preferred.
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee is preferred.
Proficiency in shell, Python, and Perl scripting is preferred.
Experience using AI technologies for data mining and Palladium or FPGA validation is preferred.

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