Wireless Design Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $122,700–$214,300 / yr
Posted: 57 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k

This role $168k

$110k most similar roles pay here $237k

This role pays less than 66% of similar roles. Most pay $167,925–$214,000 — the shaded band above. At the midpoint, this role pays about $168k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Wireless Design Verification Engineer

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As a Wireless Design Verification Engineer, you will join the wireless silicon development team to perform pre-silicon RTL verification of the wireless MAC and its interfaces with the rest of the wireless SoC. You will collaborate with DV methodologists, designers, and communication systems engineers to develop reusable testbenches and verification environments using metric-driven methodologies. Your daily work involves creating verification plans from specifications, building UVM libraries, executing directed and constrained random tests, and managing bug tracking. You will also create coverage models and utilize machine learning and AI technologies for data mining and analysis. The role requires proficiency in Verilog, SystemVerilog, UVM, SystemVerilog Assertion, shell, Python, and Perl scripting. Technical focus areas include MAC, PHY, DMA, AMBA bus, and wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee while supporting validation using Palladium and FPGA.

Skills

SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium Machine Learning AI Bluetooth WLAN Zigbee UWB AMBA RTL Constrained Random Testing

What you'll do

Create verification plans from specifications and refine them to achieve coverage targets.
Build block and subsystem level testbenches using UVM libraries and best-in-class methodologies.
Develop and execute directed and constrained random tests to identify design flaws.
Manage bug tracking and work with designers to resolve issues found during testing.
Create and analyze coverage models while adding test cases to increase verification depth.
Utilize machine learning and AI technologies to identify design and testbench issues.
Support MAC subsystem validation using Palladium or FPGA platforms.
Improve overall DV methodology and flow through continuous process improvement.

What we're looking for

A bachelor's degree is required.
3+ years of verification experience for wireless or wired communication blocks/subsystems.
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
Experience with ASIC verification flows including testbench development, constrained random testing, and coverage analysis.
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
Proficiency in shell, Python, and Perl scripting.
Experience using AI technologies for data mining and analysis.
Experience with Palladium or FPGA validation.

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