below marketmost similar roles pay hereabove market
This role pays less than
72%
of similar roles. Most pay
$168,500–$241,750
— the blue band above.
At the midpoint, this role pays about
$168k
versus about
$205k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
JOB TITLE: Wireless Design Verification Engineer
The Wireless Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification of the wireless MAC and its interfaces within the wireless SoC. The role involves collaborating with DV methodologists, designers, and communication systems engineers to develop reusable testbenches and verification environments using metric-driven verification. Key responsibilities include creating verification plans from specifications, building UVM libraries, executing constrained random tests, and managing bug tracking. The candidate will utilize Verilog, SystemVerilog, UVM, SystemVerilog Assertion, and shell, Python, and Perl scripting. Additionally, the role requires using machine learning and AI technologies for data mining and analysis. Technical experience must include ASIC verification flows, wireless protocols like Bluetooth, UWB, WLAN, or Zigbee, and validation using Palladium or FPGA hardware.
Create verification plans from specifications to achieve specific coverage targets for the MAC subsystem.
Build block and subsystem level testbenches using UVM libraries and best-in-class DV methodology.
Develop and execute directed and constrained random tests to identify and debug design failures.
Create and analyze coverage models to identify gaps and add necessary test cases.
Use machine learning and AI technologies to identify design issues and ensure verification quality.
Support MAC subsystem validation using Palladium emulators and FPGA platforms.
Manage bug tracking and work with designers to drive the closure of identified issues.
What we're looking for
Minimum requirement of a bachelor's degree.
3+ years of verification experience of wireless/wired communication block/subsystem (preferred).
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion (preferred).
Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage (preferred).
Verification experience of MAC, PHY, DMA, timer, AMBA bus and fabric, or encryption/decryption engine (preferred).
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee (preferred).
Proficient in shell, Python, and Perl scripting (preferred).
Experience using AI technologies in data mining/analysis and Palladium/FPGA validation (preferred).