Wireless Design Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $129,300–$225,300 / yr
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k

This role $177k

$115k $265k

below market most similar roles pay here above market

This role pays less than 63% of similar roles. Most pay $168,500–$241,750 — the blue band above. At the midpoint, this role pays about $177k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3595 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2772 roles with salary data.

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At a glance

TL;DR · Wireless Design Verification Engineer

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The Wireless Design Verification Engineer joins the Wireless Connectivity team to ensure first-time-right silicon success for next-generation WiFi SoCs. This role focuses on verifying radio digital controllers and RF subsystems, specifically managing complex radio control and transceiver paths including PLLs, DAC/ADC data paths, power management, and co-existence mechanisms. You will develop UVM testbench environments, bus functional models, and infrastructure while implementing constrained random scenarios to exercise radio protocols and state machine interactions. Key technical requirements include proficiency in SystemVerilog, Verilog, VHDL, and Python for automation. You will also utilize mixed-signal verification techniques such as real-number modeling to validate radio control paths. The work involves bridging digital and RF/analog domains to solve complex wireless performance challenges through comprehensive test planning and coverage closure.

Skills

SystemVerilog UVM Python Verilog VHDL Mixed-Signal Verification Real-Number Modeling Assertion-Based Verification RTL Simulation Bash Perl ASIC Verification Functional Coverage Digital Design

What you'll do

Verify radio digital controllers and subsystems from initial test planning through feature closure.
Develop UVM testbench environments, bus functional models, and infrastructure for radio control and datapath subsystems.
Implement constrained random scenarios to exercise radio protocols, control sequences, and state machine interactions.
Perform mixed-signal verification using SystemVerilog analog behavioral and real-number models to validate radio control paths.
Drive verification closure by tracking regressions, debugging functional issues, and addressing coverage gaps.
Develop Python automation to support verification flows and regression infrastructure.

What we're looking for

Understanding of ASIC verification flows with SystemVerilog, including UVM testbench development, scenario creation, and RTL simulation.
Experience developing verification environments, bringing up designs in simulation, and debugging functional issues.
Experience with digital design fundamentals using Verilog or VHDL.
Experience with scripting languages such as Python or similar.
Experience with digital controllers, subsystems, or data paths (preferred).
Experience with constrained random testing, functional coverage, UVM methodology, and assertion-based verification (preferred).
Exposure to mixed-signal modeling, real-number modeling, or RF/analog system design (preferred).
Bachelor’s degree.

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