Verification Infrastructure Engineer, Testbench Architecture

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Fishkill, NY
Salary
$121,680–$182,520 / yr
Posted
11 days ago
Freshness
Confirmed live yesterday
Closes
Aug 31, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $187k
This role $152k
$109k most similar roles pay here $243k

This role pays less than 81% of similar roles. Most pay $168,500–$206,450 — the shaded band above. At the midpoint, this role pays about $152k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Verification Infrastructure Engineer, Testbench Architecture

The Verification Infrastructure Engineer- Testbench Architecture joins the team to provide technical expertise for the functional verification strategy of next-generation microprocessor designs. This role focuses on modernizing Zen architecture verification infrastructure by simplifying design verification methodologies and reducing development complexity. The engineer will architect, develop, and maintain reusable C++ verification libraries for stimulus generation, model checking, and scalable workflows while leading strategic initiatives like AVF replacement and testbench modernization. Key responsibilities include collaborating with CPU design, architecture, and CAD teams to deploy scalable solutions and improving overall validation quality across multiple programs. Required skills include proficiency in C++, object-oriented design, version control, and continuous integration. The role addresses the technical challenge of managing complex processor and microarchitecture development from concept through execution while ensuring testbench maintainability and infrastructure scalability for future processor programs.

What you'll do

  • Modernize Zen architecture verification infrastructure by simplifying design verification methodologies and reducing complexity.
  • Architect, develop, and maintain reusable C++ verification libraries for stimulus generation and model checking.
  • Drive productivity improvements through standardized, reusable verification frameworks and automation across processor programs.
  • Lead strategic infrastructure initiatives including AVF replacement efforts and next-generation testbench modernization.
  • Collaborate with CPU design, architecture, and CAD teams to deploy scalable verification solutions.
  • Identify opportunities to improve verification efficiency, testbench maintainability, and validation quality.
  • Provide technical leadership and mentorship while influencing verification methodology and long-term infrastructure roadmaps.

What we're looking for

  • Candidates should possess a BS or MS degree in Computer Science or Electrical Engineering.
  • Extensive experience in CPU, SoC, or IP Design Verification is required.
  • Proven expertise in developing verification infrastructure and reusable libraries using C++.
  • Experience with stimulus generation, model checking, reference model development, and automation techniques is required.
  • Strong knowledge of testbench architecture, scalability, and infrastructure modernization initiatives is required.
  • Experience supporting complex processor or microarchitecture programs from concept through execution is preferred.
  • Familiarity with AVF analysis or related resilience and validation methodologies is preferred.
  • Strong software engineering skills including object-oriented design, code quality, and continuous integration are required.

More like this

Similar roles

Hardware Validation Engineer II

F5 Inc

Remote (Spokane Valley, WA) 10 days ago $101,600$152,400
PCIe DDR5 Ethernet FPGA Python MATLAB LabVIEW SI/PI Analysis HyperLynx Sigrity VNA BERT Oscilloscope Intel Xeon AMD Versal JEDEC PCI-SIG IEEE
2+ yrs exp Remote

Verification Platform Engineer, Platform Architecture

Apple Inc

Cupertino, CA 8 days ago $184,700$324,800
SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C high-performance computing Co-simulation Hardware Emulation Linting Static Analysis Waveform Debugging Testbench Architecture
10+ yrs exp

Verification Platform Engineer, Platform Architecture

Apple Inc

Cupertino, CA 8 days ago $150,400$225,300
SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C High-Performance Computing Co-simulation Hardware Emulation Linting Static Analysis Waveform Debugging Testbench Architecture
3+ yrs exp

Verification Platform Engineer, Platform Architecture

Apple Inc

Austin, TX 8 days ago
SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C High-Performance Computing Co-simulation Hardware Emulation Linting Static Analysis Waveform Debugging Testbench Architecture
10+ yrs exp

Verification Platform Engineer, Platform Architecture

Apple Inc

Austin, TX 8 days ago
SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C High-Performance Computing Co-simulation Hardware Emulation Linting Static Analysis Waveform Debugging Testbench Architecture
3+ yrs exp