Verification Platform Engineer, Platform Architecture

Apple Inc

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Work type: On-site
Location: Austin, TX
Posted: 54 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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TL;DR · Verification Platform Engineer, Platform Architecture

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The Verification Platform Engineer, Platform Architecture joins the Platform Architecture group to develop high-performance verification systems for next-generation Apple silicon. This role bridges platform technology with design verification methodology to improve simulation throughput for design verification workflows. You will own engagements with silicon engineering groups to evaluate, integrate, and maintain high-performance RTL simulation tooling while modifying testbenches and design RTL for efficiency. Key responsibilities include designing infrastructure improvements for faster simulation turnaround and diagnosing issues using internal and external EDA tools. Required skills include SystemVerilog, C++, and scripting in Perl or Python. Preferred qualifications include experience with UVM, DPI-C, Logic Equivalence Checking, and waveform debugging. You will solve technical problems related to pre-silicon validation by applying principles from hardware emulation to simulation solutions.

Skills

SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C Testbench Architecture High-Performance Computing HPC Static Analysis Waveform Debugging Simulation Emulation Co-simulation

What you'll do

Evaluate, integrate, and maintain high-performance RTL simulation tooling for silicon engineering groups.
Modify testbench and design RTL to improve tool compatibility and simulation efficiency.
Use EDA tools to diagnose issues and explore design alternatives.
Design and integrate infrastructure improvements to accelerate simulation turnaround after RTL changes.
Develop agentic pipelines and skills to enable AI productivity for other engineers.
Optimize simulation throughput for DV workflows through testbench design and platform R&D.

What we're looking for

Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
Experience with SystemVerilog and EDA tooling.
Experience with software development using C++ and scripting using Perl or Python.
Master’s degree in Computer Engineering, Electrical Engineering, or another hardware-related field (preferred).
3+ years of relevant experience (preferred).
Deep hands-on experience in Design Verification methodologies including UVM, DPI-C, and testbench architecture (preferred).
Experience applying LEC, linting, static analysis, waveform debugging, and simulation/emulation flows (preferred).
Experience with software optimization, high-performance computing, co-simulation architectures, or hardware acceleration (preferred).

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