Verification Platform Engineer, Platform Architecture

Apple Inc

Confirmed live yesterday High trust

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Work type
On-site
Location
Austin, TX
Posted
8 days ago
Freshness
Confirmed live yesterday

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Similar $177k
$111k most similar roles pay here $232k

This listing doesn't post a salary. Most similar roles pay $151,000–$202,561.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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TL;DR · Verification Platform Engineer, Platform Architecture

The Verification Platform Engineer, Platform Architecture joins the Platform Architecture group to develop high-performance verification systems that accelerate the development of Apple silicon by extending hardware emulation principles into pre-silicon validation. This role bridges platform technology with design verification methodology and tooling to improve simulation throughput for various workflows. You will own engagements with silicon engineering groups to evaluate, integrate, and maintain RTL simulation tools while modifying testbenches and design RTL for efficiency. Key responsibilities include designing infrastructure improvements for faster turnaround after RTL changes and diagnosing issues using EDA tools like Logic Equivalence Checking and wave dumps. Required skills include SystemVerilog, C++, Perl, or Python scripting, and experience with UVM, DPI-C, and testbench architecture. The role focuses on solving technical challenges in simulation throughput, hardware representation, and high-performance computing for next-generation silicon products.

What you'll do

  • Evaluate, integrate, and maintain high-performance RTL simulation tooling with silicon engineering groups.
  • Modify testbench and design RTL to improve tool compatibility and simulation efficiency.
  • Utilize EDA tools like LEC and wave dumps to diagnose issues and explore design alternatives.
  • Design and integrate infrastructure improvements to accelerate simulation turnaround after RTL changes.
  • Develop advanced verification methodologies including UVM, DPI-C, and testbench architecture.
  • Build agentic pipelines and other systems to enable AI productivity for engineering teams.
  • Optimize software performance using C++, Python, or Perl for hardware verification workflows.

What we're looking for

  • Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
  • Master's degree in Computer Engineering, Electrical Engineering, or another hardware-related field is preferred.
  • 3+ years of relevant experience are preferred.
  • Experience with SystemVerilog and EDA tooling.
  • Experience with software development using C++ and scripting using Perl or Python.
  • Deep hands-on experience in Design Verification methodologies including UVM, DPI-C, and testbench architecture.
  • Experience with LEC, linting/static analysis tools, waveform debugging, and simulation/emulation flows.
  • Strong understanding of SystemVerilog simulation semantics and hardware representation.

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