Verification Platform Engineer, Platform Architecture

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $150,400–$225,300 / yr
Posted: 54 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $192k

This role $188k

$124k $246k

below market most similar roles pay here above market

This role pays more than 63% of similar roles. Most pay $169,550–$214,000 — the blue band above. At the midpoint, this role pays about $188k versus about $192k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Verification Platform Engineer, Platform Architecture

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Verification Platform Engineer, Platform Architecture joins the Platform Architecture group to develop high-performance verification systems for Apple silicon. This role bridges platform technology with design verification methodology to improve simulation throughput for development workflows. The engineer will own engagements with silicon engineering groups to evaluate and maintain RTL simulation tooling, modify testbenches and design RTL for efficiency, and design infrastructure improvements for faster simulation turnaround. Key responsibilities include diagnosing issues using Logic Equivalence Checking, wave dumps, and design libraries. Required skills include SystemVerilog, C++, and scripting in Perl or Python. Preferred qualifications include UVM, DPI-C, and experience with linting, static analysis, and hardware acceleration. The work involves solving pre-silicon validation problems by extending hardware emulation principles to simulation solutions.

Skills

SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C High-Performance Computing Hardware Emulation Static Analysis Waveform Debugging Testbench Architecture Co-simulation

What you'll do

Own engagements with silicon engineering groups to evaluate, integrate, and maintain high-performance RTL simulation tooling.
Modify testbench and design RTL to improve tool compatibility and simulation efficiency.
Use internal and external EDA tools to diagnose issues and explore design alternatives.
Design and integrate infrastructure improvements to achieve faster simulation turnaround after RTL changes.
Develop agentic pipelines, graphs, or skills to enable AI productivity for other engineers.
Prototype solutions to improve simulation throughput for Design Verification workflows.

What we're looking for

Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
Experience with SystemVerilog and EDA tooling.
Experience with software development using C++ and scripting using Perl or Python.
Master’s degree in Computer Engineering, Electrical Engineering, or another hardware-related field (preferred).
3+ years of relevant experience (preferred).
Deep hands-on experience in Design Verification methodologies including UVM, DPI-C, and testbench architecture (preferred).
Experience applying LEC, linting, static analysis, waveform debugging, and simulation/emulation flows (preferred).
Experience with software optimization, high-performance computing, co-simulation, or hardware acceleration (preferred).

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