Verification Platform Engineer, Platform Architecture

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$150,400–$225,300 / yr
Posted
8 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $177k
This role $188k
$110k most similar roles pay here $238k

This role pays more than 72% of similar roles. Most pay $151,000–$202,561 — the shaded band above. At the midpoint, this role pays about $188k versus about $177k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Verification Platform Engineer, Platform Architecture

The Verification Platform Engineer, Platform Architecture joins the Platform Architecture group to develop high-performance verification systems and tools for next-generation silicon. This role bridges platform technology with design verification methodology by prototyping solutions to improve simulation throughput for development workflows. Key responsibilities include owning engagements with silicon engineering groups to integrate RTL simulation tooling, modifying testbenches and design RTL for efficiency, and designing infrastructure improvements for faster turnaround after changes. The candidate will utilize SystemVerilog, C++, Perl, or Python while engaging with EDA tools such as Logic Equivalence Checking, wave dumps, and design libraries. The work focuses on pre-silicon validation by applying hardware emulation principles to simulation solutions. Essential skills include UVM, DPI-C, testbench architecture, waveform debugging, and experience with high-performance computing or co-simulation architectures to solve complex hardware verification challenges.

What you'll do

  • Evaluate, integrate, and maintain high-performance RTL simulation tooling with silicon engineering groups.
  • Modify testbench and design RTL to improve tool compatibility and simulation efficiency.
  • Utilize EDA tools like LEC and wave dumps to diagnose issues and explore design alternatives.
  • Design and integrate infrastructure improvements to accelerate simulation turnaround after RTL changes.
  • Develop agentic pipelines and other technologies to enable AI productivity for engineers.
  • Prototype solutions to improve simulation throughput for design verification workflows.

What we're looking for

  • Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
  • Master's degree in Computer Engineering, Electrical Engineering, or another hardware-related field is preferred.
  • 3+ years of relevant experience are preferred.
  • Experience with SystemVerilog and EDA tooling.
  • Experience with software development using C++ and scripting using Perl or Python.
  • Deep hands-on experience in Design Verification methodologies including UVM, DPI-C, and testbench architecture.
  • Experience with LEC, linting/static analysis tools, waveform debugging, and simulation/emulation flows.
  • Experience with software optimization, high-performance computing (HPC), co-simulation architectures, or hardware acceleration.

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