Verification Platform Engineer, Platform Architecture

Apple Inc

Confirmed live yesterday Trusted

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Work type: On-site
Location: Austin, TX
Posted: 54 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $192k

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Verification Platform Engineer, Platform Architecture

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The Verification Platform Engineer, Platform Architecture joins the Platform Architecture group to develop high-performance verification systems for next-generation Apple silicon. This role bridges platform technology with design verification methodology by prototyping solutions to improve simulation throughput for design verification workflows. Key responsibilities include owning engagements with silicon engineering groups to integrate high-performance RTL simulation tooling, modifying testbenches and design RTL for efficiency, and designing infrastructure improvements for faster simulation turnaround. The position requires proficiency in SystemVerilog, C++, Perl, and Python, alongside experience with EDA tools such as Logic Equivalence Checking, wave dumps, and design libraries. Candidates must understand UVM, DPI-C, and simulation semantics to solve pre-silicon validation problems by extending principles from hardware emulation to simulation solutions.

Skills

SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C Testbench Architecture High-Performance Computing HPC Hardware Emulation Static Analysis Waveform Debugging Co-simulation Linting

What you'll do

Evaluate, integrate, and maintain high-performance RTL simulation tooling with silicon engineering groups.
Modify testbench and design RTL to improve tool compatibility and simulation efficiency.
Use EDA tools to diagnose issues and explore design alternatives.
Design and integrate infrastructure improvements to accelerate simulation turnaround after RTL changes.
Develop agentic pipelines and skills to enable AI productivity for other engineers.
Prototype solutions to improve simulation throughput for design verification workflows.

What we're looking for

Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
Experience with SystemVerilog and EDA tooling.
Experience with software development using C++ and scripting using Perl or Python.
Master’s degree in Computer Engineering, Electrical Engineering, or another hardware-related field (preferred).
10+ years of relevant experience (preferred).
Deep hands-on experience in Design Verification methodologies including UVM, DPI-C, and testbench architecture (preferred).
Experience applying LEC, linting, static analysis, waveform debugging, and simulation/emulation flows (preferred).
Experience with software optimization, high-performance computing, co-simulation architectures, or hardware acceleration/emulation (preferred).

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