Design Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 45 days ago

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How this pay compares to similar roles

Similar $175k

$126k most similar roles pay here $228k

This listing doesn't post a salary. Most similar roles pay $142,450–$208,200.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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Join our dynamic team as a Design Verification Engineer and play a pivotal role in ensuring the flawless production of first silicon for IP designs. You will develop comprehensive test plans, establish robust DV methodologies, and create scalable verification environments using SystemVerilog and UVM. Your daily tasks include developing infrastructure to stress-test designs, fixing regression failures, and leveraging large language models (LLMs) to enhance verification efficiency. This position demands expertise in object-oriented programming, simulation tools, and coverage collection techniques, with a preference for experience in power-aware verification methodologies and scripting languages like Python or Perl. As part of our cutting-edge hardware group, you will tackle complex challenges at the SoC level, contributing to products that impact millions globally.

Skills

SystemVerilog UVM Python Perl TCL LLMs OOP PCIe USB DDR UPF Formal Verification Emulation Technologies

What you'll do

Develop detailed test and coverage plans based on micro-architecture.
Establish DV methodology suitable for IP designs to ensure scalability.
Create verification environment including stimulus, checkers, assertions, trackers.
Implement regression testing and debug failures in the design.
Track and report progress using various metrics like bugs and coverage.

What we're looking for

Minimum 3 years of proven experience in design verification or equivalent education.
Strong knowledge of OOP, SystemVerilog, and UVM for developing scalable test-benches.
Proven experience with verification methodologies and tools including simulators and coverage collection.
Experience using LLMs to enhance verification efficiency and quality.
Familiarity with power-aware verification methodology (UPF) is preferred.
Knowledge of scripting languages like Python or Perl beneficial for automation tasks.

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