Design Verification Engineer

Broadcom

Quick summary

Work type: On-site
Location: Broomfield, CO · West Bernardo, CA · Fort Collins, CO · Innovation Drive, CA · Alton Parkway Bldg 1, CA
Salary: $108,000–$172,800 / yr
Posted: 47 days ago
Closes: Oct 18, 2026
Nearby: 95 roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $183k

This role $140k

$95k most similar roles pay here $232k

This role pays less than 82% of similar roles. Most pay $152,875–$213,375 — the shaded band above. At the midpoint, this role pays about $140k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 105 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 103 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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Broadcom's ASIC Products Division seeks a senior Design Verification Engineer to join their team, responsible for defining verification plans and environments for complex digital and mixed-signal IP blocks. The role involves developing test cases, conducting coverage analysis, and debugging at both RTL and gate-level using SystemVerilog and UVM. Candidates must have experience with Synopsys, Cadence, and Mentor simulation tools, as well as Perl/Python scripting and version control systems like git. Ideal candidates will also possess knowledge of formal verification concepts and expertise in emulation platforms such as Palladium or Veloce, contributing to the development of scalable verification environments for high-complexity ASIC projects.

Skills

SystemVerilog UVM SVA Perl Python Tcl git DesignSync Synopsys Cadence Mentor Palladium Veloce Zebu Xilinx ICL PDL Tessent

What you'll do

Define verification plans and environment architecture for complex digital and mixed-signal IP blocks.
Develop test cases, test bench components, and perform coverage analysis to ensure thorough testing.
Debug simulation failures at RTL and gate-level using knowledge of netlists and SDF formats.
Collaborate with design teams and EDA vendors on modeling and verification tasks.
Implement advanced verification methodologies such as UVM and SystemVerilog Assertions.
Analyze schematic diagrams of analog/mixed-signal circuits for verification purposes.

What we're looking for

6+ years of verification experience for complex digital and mixed-signal circuits.
Proficient in SystemVerilog, UVM, and advanced verification methodologies.
Experience with Synopsys, Cadence, and Mentor simulation tools.
Strong debugging skills at RTL and gate-level netlists.
Knowledgeable in Perl/Python scripting and version control systems.
Ability to develop complex, reusable, and scalable verification environments.
Excellent problem-solving and communication skills.

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