SIPI Architect for High-Speed SerDes

As the SIPI Architect for High-Speed SerDes, you will join the SoC development team to define and own the end-to-end signal and power integrity architecture for cutting-edge high-speed SerDes links. You will be responsible for guiding technical direction across cross-functional teams including circuit design, packaging, system hardware, and validation while leading system-level trade-off analyses to optimize performance, power, and cost from silicon to system levels. Your work involves overseeing comprehensive modeling, simulation, and silicon correlation to ensure robust interconnect performance. You will utilize expertise in 112G/224G SerDes technologies, Ethernet, PCIe, UAL, and CXL protocols. The role addresses technical challenges in high-performance computing environments, involving advanced packaging like 2.5D/3D integration, co-packaged optics, and system-level power integrity for high-power ASICs to solve complex interconnect problems.