SIPI Architect for High-Speed SerDes

What you'll do

• Define and own the end-to-end signal and power integrity architecture for high-speed SerDes links.
• Drive technical direction and build consensus across circuit design, packaging, hardware, and validation teams.
• Lead system-level trade-off analyses to optimize performance, power, and cost across silicon and package levels.
• Provide expert guidance on future interconnect technologies and advanced packaging for the technology roadmap.
• Oversee comprehensive modeling, simulation, and silicon correlation to ensure robust interconnect design.
• Develop and champion next-generation SIPI methodologies and best practices for design and analysis.

What we're looking for

• BS degree and 10+ years of relevant industry experience.
• MS or PhD in Electrical Engineering or a related field with 10+ years of experience (preferred).
• Deep expertise in system-level SIPI for high-speed SerDes (112G/224G and beyond) (preferred).
• Proven experience architecting solutions for high-performance interconnects using standards such as Ethernet, PCIe, UAL, and CXL (preferred).
• Expertise in end-to-end channel modeling, link budget analysis, and statistical or time-domain simulation (preferred).
• In-depth understanding of SerDes TX/RX equalization, clocking, and power delivery trade-offs (preferred).
• Experience leading cross-functional teams to drive technical consensus across silicon, packaging, and system hardware groups (preferred).
• Familiarity with advanced packaging, co-packaged optics, and system-level PDN or thermal co-design (preferred).