Senior Package Layout Engineer

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Chandler, AZ
Salary
$161,500–$218,500 / yr
Posted
27 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $190k
This role $190k
$138k most similar roles pay here $234k

This role pays more than 56% of similar roles. Most pay $162,050–$217,981 — the shaded band above. At the midpoint, this role pays about $190k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

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At a glance

TL;DR · Senior Package Layout Engineer

As a Senior Package Layout Engineer within the System-in-Package team, you will contribute to implementing next-generation SoCs for the IoT, Automotive, and Compute spaces. You will be responsible for the design, development, and verification of package designs while navigating loosely defined problems and adapting to frequent design changes. Your daily work involves developing IC Package Layouts for high speed signal and high power devices, conducting feasibility studies regarding size, cost, and system performance, and implementing routing, stack-up creation, reference planes, and power distribution. You will utilize the Cadence APD or SiP tool suite and Allegro toolsets to execute these tasks. The role requires expertise in 2.5D and 3D package systems with specific SI/PI requirements. You will also provide guidance on methodologies to improve team efficiency and drive standardization across the department.

What you'll do

  • Develop IC package layouts for high-speed signals and high-power devices using best practices.
  • Conduct feasibility studies to evaluate package goals regarding size, cost, and system performance.
  • Implement package routing, stack-up creation, reference planes, and power distribution.
  • Utilize Cadence APD or SiP tool suites for layout design and implementation.
  • Resolve complex technical design problems independently.
  • Provide guidance and feedback on methodologies to improve overall team efficiency.
  • Drive standardization of methods to improve department-wide processes.

What we're looking for

  • An Electrical Engineering degree or equivalent work experience.
  • Experience with 2.5D and 3D package systems and their SI/PI requirements.
  • 3-5 years of recent experience in the use of Cadence APD & Allegro toolsets.
  • Ability to develop IC Package Layouts for high speed signal and high power devices.
  • Ability to conduct feasibility studies for size, cost, and system performance goals.
  • Familiarity with EDA vendor collaboration, tool evaluation, and issue resolution (preferred).
  • Good verbal, written communication and presentation skills (preferred).
  • Ability to optimize design methodologies in packaging design (preferred).

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