Staff STA Engineer

What you'll do

• Own full chip and block level timing closure throughout the entire project cycle.
• Manage timing constraints for functional and test modes across different logical hierarchical levels.
• Resolve sophisticated timing issues for major building blocks of complex SoCs.
• Generate ECOs at both the block and top levels.
• Implement timing and functional ECOs in coordination with relevant teams.
• Develop and manage timing constraints for 5nm and 3nm technologies.
• Utilize automation scripts in Perl, Tcl, or Python to streamline timing tasks.

What we're looking for

• Work experience of 6+ years in Timing convergence.
• Experience in industry standard STA tools and methodologies.
• Knowledge of timing corners/modes including DFT, process variations and signal integrity issues.
• Work experience on timing closure for multi power domain designs.
• Experience in collaborating across silicon engineering groups and with EDA vendors.
• Experience in constraints development and timing closure on 5nm or 3nm technologies.
• Strong automation skills in Perl, Tcl, and Python.
• Masters or equivalent experience in Electrical Engineering (preferred).