Senior Implementation Engineer

Amazon Inc

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Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $213,000–$287,500 / yr
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Above market

How this pay compares to similar roles

Similar $177k

This role $250k

$126k $305k

below market most similar roles pay here above market

This role pays more than 99% of similar roles. Most pay $167,162–$187,250 — the blue band above. At the midpoint, this role pays about $250k versus about $177k for comparable roles.

Based on 240 similar postings.

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About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 627 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 621 roles with salary data.

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At a glance

TL;DR · Senior Implementation Engineer

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The Sr. Implementation Engineer joins the Amazon Leo team to develop digital chip SOCs for satellite communications and gateways. This role focuses on building a groundbreaking wireless solution for low-latency broadband connectivity. You will work with the ASIC design team to develop chip power intent using UPF, validate UPF at RTL and netlist levels, and establish logic and physical synthesis flows for various technology nodes. Key responsibilities include creating timing constraints, performing STA and LEC on netlists, and ensuring proper top-level integration of analog blocks with RFIC teams. You will also lead timing sign-off for post-P&R databases and verify IR/EM results for DFM criteria. Required skills include ASIC implementation experience, synthesis, STA, P&R for deep sub-micron nodes, and multi-power island designs.

Skills

ASIC Implementation Synthesis STA P&R UPF RTL DFT IR/EM DFM LEC CMOS Physical Design Timing Sign-off Formal Connectivity Checks

What you'll do

Develop chip power intent using UPF and validate it at the RTL and netlist levels.
Establish logic and physical synthesis flows for various technology nodes.
Create timing constraints by analyzing designs with the ASIC design and DFT teams.
Perform Static Timing Analysis (STA) and Logic Equivalence Checking (LEC) on netlists.
Verify top-level analog block integration and perform formal connectivity checks with RFIC teams.
Manage netlist hand-offs to P&R teams and participate in flow reviews to optimize PPA.
Lead timing sign-off for the post-P&R database.
Verify IR/EM results to ensure the chip meets required Design for Manufacturing (DFM) criteria.

What we're looking for

Bachelor's degree in Electrical Engineering or a related field.
8+ years of experience in ASIC implementation, including synthesis, STA, and P&R for deep sub-micron nodes (preferably 16nm or smaller).
Experience leading or solely developing methodology and scripts for physical synthesis.
Proven track record of taping out chips for high volume production.
Familiarity with implementing chips with multiple power islands and power gating.
Master's or Ph.D. degree in Electrical or Communications Engineering (preferred).
10+ years of experience in ASIC implementation (preferred).
Export control laws and regulations, candidates.