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Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
589 open roles
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Listed pay typically runs
$147,900–$221,900
across 563 roles with salary data.
As a Software Engineer — RISC-V Random Test Generator within the CPU Engineering group, you will contribute to a Python-based random test generation framework and a companion assembler library. This role involves developing a JIT-style, simulator-coupled generator that produces ELF binaries to exercise the RVA23.1 ISA, including privileged modes, virtual memory, and cryptography extensions. You will implement new generation objects for RISC-V extensions, add instruction encodings to the assembler, and tune generation themes to improve RTL coverage. Key responsibilities include working within the privileged-software stack, including exception handlers and page-table builders, while triaging failures with ISS and RTL verification engineers. Required skills include Python 3, generator-based coroutines, and deep knowledge of RISC-V ISA encoding, CSR semantics, and memory models.
What does a Software Engineer earn in California?
Median $214500 from 1223 postings across 76 companies.
Implement new generation objects for RISC-V extensions and complex data/control-flow idioms.
Add instruction forms and encodings to the Python assembler library.
Verify bit-level correctness of the assembler against the RISC-V ISA specification.
Write and tune generation themes to improve RTL coverage through knob-driven test profiles.
Develop privileged-software stack components including exception handlers and page-table builders.
Triage failures with ISS and RTL verification engineers to add targeted regression scenarios.
Adjust constraint logic for register allocators, address-space managers, and data fillers.
What we're looking for
Bachelor's degree and 4+ years of relevant engineering experience, Master's degree and 3+ years, or PhD and 2+ years of relevant engineering experience.
2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
Solid Python 3 skills including generator-based coroutines and object-oriented design patterns.
Working knowledge of the RISC-V ISA, including instruction encoding, CSR semantics, privilege levels, and memory models.
Working knowledge of x86 or ARM ISA as an alternative to RISC-V.
Familiarity with virtual memory (Sv39/Sv48), PMP, and trap/interrupt handling.
Exposure to random test generation flows or ISS/RTL co-simulation (preferred).
Experience with compiler development, hypervisor/AIA/IMSIC architectures, or constraint-propagation libraries (preferred).
C++
RISC-V
Python
RTL Co-simulation
QEMU
Spike
gem5
GDB
ELF
Linux
Computer Architecture
Hardware Verification
Embedded Systems
Operating Systems
Compilers