Software Engineer, RISC-V Random Test Generator

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $167,100–$250,700 / yr
Posted: 2 days ago
Freshness: Confirmed live yesterday
Closes: Mar 8, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $181k

This role $209k

$131k most similar roles pay here $264k

This role pays more than 75% of similar roles. Most pay $152,693–$208,900 — the shaded band above. At the midpoint, this role pays about $209k versus about $181k for comparable roles.

Based on 240 similar postings.

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About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Software Engineer, RISC-V Random Test Generator

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As a Software Engineer — RISC-V Random Test Generator, you will join the CPU Engineering team to develop a Python-based random test generation framework and its companion assembler library for a RISC-V CPU design-verification toolchain. You will build new generation objects for RISC-V extensions, implement instruction forms in the assembler, and tune knob-driven test profiles to improve RTL coverage. Your daily work involves navigating the privileged-software stack, including exception handlers, page-table builders, and PMP configurations. The role requires proficiency in Python 3, specifically with generator-based coroutines and object-oriented design patterns. You will apply knowledge of the RISC-V ISA, memory models, and virtual memory to solve complex verification problems. Key technical areas include bit-accurate instruction encoding, RTL co-simulation, and managing constraint logic for register allocators and address-space managers within the RVA23.1 architecture.

What does a Software Engineer earn in California?

Median $214000 from 775 postings across 63 companies.

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Skills

RISC-V Python ELF RTL Verification ISS Compiler Development Virtual Memory JIT Co-simulation constraint-propagation x86 ARM

What you'll do

Implement new generation objects for RISC-V extensions and complex data/control-flow scenarios.
Add instruction forms and encodings to the Python assembler library while verifying bit-level correctness.
Write and tune knob-driven test profiles to improve RTL coverage.
Develop privileged-software stack components including exception handlers, page-table builders, and PMP configurations.
Triage failures with verification engineers to add targeted regression scenarios.
Adjust constraint logic for register allocators, address-space managers, and data fillers.

What we're looking for

Bachelor's degree with 4+ years of experience, Master's with 3+ years, or PhD with 2+ years in a relevant engineering field.
2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
Solid Python 3 skills including generator-based coroutines and object-oriented design patterns.
Working knowledge of the RISC-V ISA, including instruction encoding, CSR semantics, privilege levels, and memory models.
Familiarity with virtual memory, PMP, and trap/interrupt handling.
Experience in compiler development or understanding of hypervisor and interrupt architecture is preferred.
Familiarity with constraint-propagation libraries is a plus.

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