Senior Software Engineer, RISC-V Instruction Set Simulator (Simulator Engineer)

Qualcomm

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Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$175,600–$263,400 / yr
Posted
25 days ago
Freshness
Confirmed live today
Closes
Mar 31, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $173k
This role $220k
$114k $279k
below market most similar roles pay here above market

This role pays more than 89% of similar roles. Most pay $150,000–$196,750 — the blue band above. At the midpoint, this role pays about $220k versus about $173k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Senior Software Engineer, RISC-V Instruction Set Simulator (Simulator Engineer)

The Senior Software Engineer — RISC-V Instruction Set Simulator (Simulator Engineer) joins the CPU Engineering team to develop a high-performance, production-grade RISC-V Instruction Set Simulator. This role serves as a golden reference model for next-generation 64-bit RISC-V processors, driving co-simulation against RTL and powering random test generation. You will translate RISC-V specification chapters into C++ code, covering integer, floating-point, vector, and security extensions. Daily tasks include maintaining the fetch, decode, and execute engines, managing memory protection, and developing unit tests to ensure simulation correctness. The role requires proficiency in C++, processor architecture, and systems programming. You will solve complex problems at the intersection of computer architecture and verification engineering, ensuring the simulator remains a fast, accurate platform for developing pre-silicon firmware and running long-running benchmarks.

What does a Software Engineer earn in California?

Median $214500 from 1193 postings across 76 companies.

See salary data

What you'll do

  • Translate RISC-V specification chapters into functional C++ code for various extensions.
  • Maintain the simulator's fetch, decode, execute, memory protection, and privilege-level logic.
  • Develop and maintain the co-simulation harness to flag differences between the ISS and RTL.
  • Write targeted unit tests to exercise individual features against expected results from the specification.
  • Contribute to and maintain simulator extensions and utilities to improve user productivity.
  • Ensure the simulator remains a bit-accurate reference model for next-generation 64-bit processors.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant engineering experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of relevant engineering experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant engineering experience.
  • Solid C++ skills and the ability to read unfamiliar codebases.
  • Knowledge of basic processor architecture, including pipelines, memory, privilege levels, and interrupts.
  • Exposure to low-level or systems programming such as embedded systems, operating systems, compilers, or hardware description.
  • Experience with RISC-V, x86, or ARM architecture (preferred).
  • Familiarity with simulators like QEMU, Spike, or gem5, and experience with GDB, ELF binaries, or Python 3+ (preferred).

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